Solid state imager with reduced number of transistors per pixel

Details Solid state imager with reduced number of transistors per pixel Solid state imager with reduced number of transistors per pixel

2006-06-06

2006-06-06

Le, Que T. (Department: 2878)

Radiant energy

Photocells; circuits and apparatus

Photocell controlled circuit

C250S208100

Reexamination Certificate

active

07057150

ABSTRACT:
A solid state imager with pixels arranged in columns and rows has the pixels are configured into groups of at least a first pixel and a second pixel, each said group sharing a pixel output transistor having a sense electrode and an output electrode and a reset transistor having a gate coupled to receive a reset signal and an output coupled to the sense electrode of the associated shared pixel output transistor. Each of the pixels has a photosensitive element whose output electrode is coupled to the sense electrode of the shared pixel output transistor and a gate electrode coupled to receive respective first and second pixel gating signals. This configuration reduces the number of FETs to two transistors for each pair of pixels, and also can achieve true correlated double sampling correction of FPN.

REFERENCES:
patent: 5898168 (1999-04-01), Gowda et al.

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