Solid state imager wherein the horizontal transfer is accomplish

Details Solid state imager wherein the horizontal transfer is accomplish Solid state imager wherein the horizontal transfer is accomplish

1992-01-17

1993-08-03

Razavi, Michael T.

Facsimile and static presentation processing

Facsimile

Recording apparatus

35821315, 35821331, 257248, H04N 314, H04N 5335

Patent

active

052334309

ABSTRACT:
A solid state imager is comprised of an imager unit composed of a plurality of sensitive units arrayed in the unit of pixels in a two-dimensional manner in the horizontal and vertical directions and vertical transfer units for transferring electric charges read-out from the sensitive units in the vertical direction at every vertical column, and a horizontal transfer unit formed of charge transfer unit group (8.sub.1, 8.sub.2, 8.sub.3, . . . ) of a plurality of bits in which a clock voltage (.phi..sub.H1) is applied to a first charge transfer unit group (8.sub.1, 8.sub.3. . . ) at every other bit including the charge transfer unit (8.sub.1) of a final bit and a clock voltage (.phi..sub.H2) is applied to a second charge transfer unit group (8.sub.2, 8.sub.4, . . . ) at every other bit of the remaining bit to transfer the electric charges supplied from the image unit in the horizontal direction, wherein a cross point between a leading edge of the clock voltage (.phi..sub.H1) and a trailing edge of the clock voltage (.phi..sub.H2) is set to be a level higher than an intermediate level between peak values of the clock voltages. Thus, a so-called electric charge flooding phenomenon from the final bit (final stage) of the horizontal transfer unit to the output circuit unit can be prevented and therefore the dynamic range of the final bit can be increased relatively.

REFERENCES:
patent: 4654713 (1987-03-01), Boucharlat et al.
patent: 4839734 (1989-06-01), Takemura
patent: 4949143 (1990-08-01), Iesaka et al.
Japanese publication JP56000096 published Jan. 6, 1981.

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