Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
1999-01-13
2001-04-03
Abraham, Fetsum (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S072000, C257S347000, C257S348000, C257S349000, C257S350000, C257S351000, C257S352000, C257S353000, C257S354000, C257S355000, C257S382000, C257S383000, C257S384000, C257S385000
Reexamination Certificate
active
06211533
ABSTRACT:
This invention relates to a thin film transistor (TFT) structure for use in, for example, imaging devices and liquid crystal display (LCD) devices. More particularly, this invention relates to a TFT structure having at least one variably doped contact layer system for reducing leakage current and increasing mobility in TFTs.
BACKGROUND OF THE INVENTION
Electronic matrix arrays find considerable application in devices such as imagers (e.g. X-ray imagers) and LCDs. Such devices typically include x and y (or row and column) address lines which are horizontally and vertically spaced apart and cross at an angle to one another thereby forming a plurality of crossover points. Associated with each crossover point is an element (i.e. pixel) to be selectively addressed. The element may be a pixel of an imager array, or alternatively a pixel of an LCD.
Typically, a switching or isolation device such as a thin film transistor (TFT) is associated with each element or pixel in order to permit individual pixels in the imager or LCD to be selectively addressed (i.e. driven in LCD applications and read in imager applications).
Structurally, TFTs typically include source, drain, and gate electrodes, with a thin film of semiconductor material (e.g. amorphous silicon or a-Si) disposed between the source and drain electrodes, and the gate electrode in proximity to the semiconductor but electrically insulated therefrom by a gate insulator. A typical bottom-gate TFT is shown, for example, in U.S. Pat. No. 5,641,974, the disclosure of which is hereby incorporated herein by reference.
Current flow through the TFT between the source and drain electrodes is controlled by the application of voltage to the gate electrode. As shown in
FIG. 1
, the application of voltage to the gate produces an electric field which accumulates a charged region in the semiconductor layer (e.g. intrinsic a-Si). This charged region forms a current conducting channel in the semiconductor through which current flows between the source and drain electrodes of the TFT. For example, when zero or a negative voltage is applied to the gate, the TFT will be in an off-state and little or no current will flow between the source and drain. However, when a positive voltage (e.g. +10 volts) is applied to the gate, this causes the conducting channel to form and permits current to flow between the source and drain electrodes of the TFT.
FIG. 1
is a symbolic diagram of a typical TFT in an LCD showing a current path from the drain terminal to the source terminal (A→B→C→D) when the n-channel TFT turns on (i.e. V
d
>0 volts, V
g
>V
th
, V
s
=0 volts). R
s
, R
d
, and R
ch
represent source series resistance, the drain series resistance, and the channel resistance, respectively. V
d
is the drain voltage. V
g
is the gate voltage. V
s
is the source voltage. V
th
is the threshold voltage (e.g. 1 volt for n-channel TFTs) which when exceeded results in the TFT being in the on-state.
Herein, the “source” electrode of a TFT will be referred to as the electrode which is to be electrically in communication with a pixel electrode (e.g. connected to a pixel electrode in an LCD or to a pixel or collector electrode in an imager). Thus, the “drain” electrode of TFTs herein will be referred to as the electrode which electrically communicates with a data or address line and which is spaced from the corresponding source electrode.
Thus, in LCD applications for example, when a voltage (e.g. +10 volts) is applied to the gate and at the same time a video voltage (e.g. +5 volts) is applied via a data address line to the drain of a TFT, the conductive channel is formed in the semiconductor layer and current flows therethrough from the drain to the source powering the pixel electrode in the LCD so as to charge the corresponding liquid crystal (LC) pixel of the display. The pixel is then in an “on-state.” In LCD applications, the source typically reaches a voltage similar to that supplied to the drain via the data line in the on-state. The amplitude of voltage applied to the drain via the data line thus determines how much voltage will be applied across the liquid crystal material in a given pixel and thus controls gray scale levels in the display. When voltage is no longer applied to the gate (or drops below V
th
), the pixel stops charging but remains on until the next frame. Unfortunately, TFT leakage current can cause current to leak from the source to the drain through the semiconductor layer when the pixel is in an on-state and the TFT is in an off-state, thereby unintentionally and undesirably changing the amount of voltage across the liquid crystal (LC) material in the pixel and adversely affecting gray scales and shading in the display (i.e. undesirable discharging of the pixel). This leakage current is an undesirable characteristic associated with conventional TFTs.
In, for example, X-ray imager applications, the source of a TFT is typically electrically connected to a collector electrode of a given pixel. The collector electrode receives a voltage which is a function of the amount of X-ray radiation received in a corresponding area of the imager. A pixel or collector electrode in an imager may receive from about 1 to 30 volts, depending upon the amount of radiation received by that area of the imager. The drain electrode in imager TFTs is typically connected to a data line having a constant voltage (i.e. virtual ground line defining a reference voltage such as 0 volts, 5 volts, or the like). When a voltage is supplied to the gate of a TFT in an imager in order to cause the TFT to go into an “on-state”, current flows from the source to the drain so that the pixel or storage capacitor may be “read” with the voltage read from the collector electrode indicating how much radiation a given area of the imager received in a frame. Again, leakage characteristics of TFTs may allow current to flow from the source to the drain when no voltage is applied to the gate thereby allowing the imager pixel (or storage capacitor) to unintentionally discharge. This is undesirable because the voltage read out when the TFT is turned on will not be directly indicative of the radiation received.
Accordingly, a TFT's leakage current is a critical parameter determining the overall image quality of both LCDs and imagers (e.g. scanners, X-ray imagers, etc.) It is known that high TFT leakage current degrades performance of a display by yielding non-uniform gray levels, crosstalk, shading, flicker, and/or image sticking, and degrades imager performance by yielding dynamic range reduction, shading, and/or non-uniform image. In typical LCD or AMLCD applications, TFTs are biased such that V
ds
ranges from 0 to 10 volts in the off-state, and V
gs
from −3 to −6 volts in the off-state. In X-ray imagers, TFTs operate at higher V
ds
values in the off-state (i.e. collector or pixel electrodes in such imagers can receive up to 30 volts in certain applications). Thus, TFTs in X-ray imagers and other imagers are in need of extremely low leakage current characteristic in order to minimize leakage when TFTs are in the off-state.
Numerous attempts have been made to minimize TFT leakage current. For example, for crystalline-silicon and polycrystalline silicon TFTs, LDD (lightly doped drain) or drain offset structures have been introduced. However, that approach requires additional process steps (i.e. photo, ion implantation, etc.).
Leakage current in amorphous silicon (a-Si) TFTs, such as that disclosed in U.S. Pat. No. 5,641,974, has been understood as follows. Firstly, bulk leakage current may be caused by hole conduction. Holes are provided via thermal generation, field enhanced thermal generation (Pool-Frenkel barrier lowering), and/or tunneling (band-to-band or trap-to-band) in the high electric field region near the source/drain. Secondly, bulk leakage current may be caused by the introduction of density-of-state peak in the upper-half of the energy band gap. Thirdly, surface leakage current may be caused by band-bending at the inte
Byun Young Hee
Lu Yiwei
Abraham Fetsum
Laff, Whitesel & Saret, Ltd.
OIS Optical Imaging Systems, Inc.
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