Solid state imager array with address line spacer structure

Details Solid state imager array with address line spacer structure Solid state imager array with address line spacer structure

1996-03-01

1997-09-02

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Amorphous semiconductor material

257 72, 257291, 257292, 257443, 257446, H01L 3100

Patent

active

056635770

ABSTRACT:
A solid state imager is provided that has a robust, high integrity upper barrier layer disposed over photosensor pixels and data address line topography in the imager. Data address line spacers disposed between the sidewalls of the data address lines and the upper barrier layer provide an inclined foundation for the upper barrier layer in the vicinity of the data address line sidewalls, thereby providing barrier layer high integrity step segments in the region of the steps around relatively thick data address lines. The address line spacers are formed from residual photosensor semiconductive material, typically amorphous silicon, which remains following the etching steps to form deposited photosensitive semiconductive material into the pixel photosensor bodies. The spacers are typically disposed in a position corresponding to the region around the corner of the data line sidewall and the underlying material of the array, and extend along the length of the data address lines and portions of the data address lines comprising the coupling to respective pixel photosensor switching devices coupled to the address line.

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patent: 5483082 (1996-01-01), Takizawa et al.
patent: 5498573 (1996-03-01), Whetten

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