Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
2000-08-11
2004-09-28
Christensen, Andrew (Department: 2615)
Television
Camera, system and detail
Solid-state image sensor
C358S483000, C348S294000
Reexamination Certificate
active
06798454
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to a solid state image sensor system and a method for driving the same. More specifically, the invention relates to a solid state image sensor system having a plurality of pixel rows and a method for driving the same.
FIG. 4
shows the construction of a solid state image sensor system having a single pixel row, and
FIG. 5
shows a time chart for transfer clocks &PHgr;
1
and &PHgr;
2
, a reset pulse RS, a clock &PHgr;
1
B in the final stage of a shift register, and an output signal OS, which are used for reading signal charges of all of picture elements (pixels) in the system of FIG.
4
.
In a pixel row
1
having a plurality of pixels “
1
”, “
2
”, “
3
”, . . . , incident light is photoelectric-transferred to generate and store signal charges. The signal charges are transferred to an analog shift register
3
via a shift gate
2
, which is arranged adjacent to the pixel row
1
, as shown by arrows.
In the analog shift register
3
, inverse-phase transfer clocks &PHgr;
1
and &PHgr;
2
are alternately applied to a transfer electrode (not shown). Thus, the signal charges are sequentially shifted to the left in the figure.
The signal charges transferred to the final stage
4
of the analog shift register
3
are sequentially given to a charge detecting part
5
in synchronism with a transfer clock &PHgr;
1
B. The charge detecting part
5
has a capacity
6
between a node ND, which is connected to the final stage
4
, and a grounding terminal to detect a voltage corresponding to the quantity of signal charges stored in the capacity
6
. This voltage is given to an output circuit
9
for amplifying the given voltage to a required level to output an output signal OS.
In addition, a reset gate transistor
7
is provided between the node ND and a reset drain
8
, to which a power supply voltage is applied. When a reset pulse RS is applied to the gate of the reset gate transistor
7
, the signal charges having been stored in the capacity
6
are discharged to the reset drain
8
.
The output signal OS varies as shown in FIG.
5
. If the reset pulse RS is given while the transfer clock &PHgr;
1
B in the final stage
4
is in a high level, a reset noise RN is generated in the output signal OS. After the reset noise RN is generated, the level of the output signal OS becomes a reference level RL. This reference level RL corresponds to an output level when no signal charge is stored in the capacity
6
. Then, when the level of the transfer clock &PHgr;
1
B becomes a low level, the signal charges are transferred from the final stage
4
to the capacity
6
to be stored therein. At this time, the difference between the reference level RL and an output level OL
1
corresponds to the quantity of the stored signal charges. Thus, the signal charges can be read out of all of pixels of the pixel row
1
.
Then, when signal charges are read out of alternate pixels of the pixels
1
,
2
,
3
, . . . , the system is driven in timing as shown in FIG.
6
. Such a technique for reading signal charges out of alternate pixels to reduce resolution is used for reducing the quantity of data, for example.
Transfer clocks &PHgr;
1
and &PHgr;
2
applied to the transfer electrode of the analog shift register
3
, and a transfer clock &PHgr;
1
B applied to the transfer electrode of the final stage
4
are the same as those when the signal charges are read out of all of the pixels as shown in FIG.
5
. It is different from
FIG. 5
that reset pulses RS given to the reset gate
7
are alternately generated.
In this case, the output signal OS outputted from the output circuit
9
is as follows. While the transfer clock &PHgr;
1
B is in a high level, after a reset noise RN is generated, the level of the output signal OS becomes the reference level RL. When the level of the transfer clock &PHgr;
1
B becomes a low level, the signal charges read out of the pixel
1
are stored in the capacity
6
, and the level of the output signal OS becomes a level OL
1
corresponding to the quantity of the stored signal charges. This level OL
1
is held until the level of the next transfer clock &PHgr;
1
B falls to the low level after it becomes the high level. When it falls to the low level, the signal charges read out of the pixel
2
are added to the capacity
6
. Thus, the level of the output signal OS becomes a level OL
1
+OL
2
corresponding to the total quantity of the signal charges of the pixels
1
and
2
.
In this case, the number of pixels, from which signal charges are read out, is reduced to half, so that the resolution is reduced to half.
When signal charges are read out of one pixel every n (n is an integer which is 2 or more) pixels, every time the level of the transfer clock &PHgr;
1
B falls from a high level to a low level, the level of the output signal OS varies so as to be sequentially OL
1
, OL
1
+OL
2
, . . . , OL
1
+ . . . +OLn. In this case, the resolution is reduced to 1
.
FIG. 2
shows the construction of a solid state image sensor system wherein two pixel rows
1
a
and
1
b
are shifted by a width corresponding to ½ pixel to be arranged in a staggered form.
In the pixels “
1
”, “
3
”, “
5
”, of the pixel row
1
a
, incident light is photoelectric-transferred, so that signal charges are generated and stored. Similarly, in the pixels “
2
”, “
4
”, “
6
”, . . . of the pixel row
1
b
, incident light is photoelectric-transferred to generate and store signal charges. The signal charges are transferred from the pixel rows
1
a
and
1
b
to analog shift registers
3
a
and
3
b
via shift gates
2
a
and
2
b
, which are arranged adjacent to the pixel rows
1
a
and
1
b
, respectively.
In the analog shift registers
3
a
and
3
b
, inverse-phase transfer clocks &PHgr;
1
and &PHgr;
2
are alternately applied to transfer electrodes (not shown). Thus, the signal charges are sequentially shifted to the left in the figure.
The signal charges transferred to the final stages
4
a
and
4
b
of the analog shift registers
3
a
and
3
b
are sequentially given to a common charge detecting part
5
in accordance with transfer clocks &PHgr;
1
B and &PHgr;
2
B, respectively. The charge detecting part
5
has a capacity
6
between a node ND, which is connected to the final stages
4
a
and
4
b
, and a grounding terminal to detect a voltage corresponding to the quantity of signal charges stored in the capacity
6
. This voltage is given to an output circuit
9
for amplifying the given voltage to a required level to output an output signal OS.
Similar to the system shown in
FIG. 4
, a reset gate transistor RS is provided between the node ND and a reset drain
8
, to which a power supply voltage is applied. When a reset pulse RS is applied to the gate of the reset gate transistor RS, the signal charges having been stored in the capacity
6
are discharged to the reset drain
8
.
In this case, the output signal OS varies as shown in FIG.
7
. If the reset pulse RS is given while the transfer clock &PHgr;
1
B in the final stage
4
a
, to which the signal charges are transferred from the pixel row
1
a
, is in a high level, a reset noise RN is generated in the output signal OS. After the reset noise RN is generated, the level of the output signal OS becomes a reference level RL. When the level of the transfer clock &PHgr;
1
B becomes a low level, the signal charges are transferred from the final stage
4
a
to the capacity
6
to be stored therein. At this time, the difference between the reference level RL and an output level OL
1
corresponds to the quantity of the stored signal charges generated from the pixel “
1
”.
Then, if the reset pulse RS is given while the transfer clock &PHgr;
2
B in the final stage
4
b
, to which the signal charges are transferred from the pixel row
1
b
, is in a high level, a reset noise RN is generated in the output signal OS. After the reset noise RN is generated, the level of the output signal OS becomes the reference level RL. When the level of the transfer clock &PHgr;
2
B becomes a low lev
Kanesaka Yoshinori
Kashiwagi Minoru
Christensen Andrew
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Tran Nhan T.
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