Solid-state image sensor having a voltage applier and signal...

Details Solid-state image sensor having a voltage applier and signal... Solid-state image sensor having a voltage applier and signal...

2011-04-12

2011-04-12

Sohn, Seung C (Department: 2878)

Radiant energy

Photocells; circuits and apparatus

Photocell controlled circuit

C340S307000

Reexamination Certificate

active

07923674

ABSTRACT:
After resetting the potential VPD of the photodiode (11) to the predetermined potential VRST, light is incident onto the photodiode (11) for a predetermined period to decrease the VPD corresponding to the amount of the incident light. After that, a declivous ramp voltage VRAMP is applied to the source terminal of the first MOS transistor (12) which is a common-source amplifier for reading out the VPD. When the voltage difference between the gate and source of the MOS transistor (12) exceeds a threshold voltage, the MOS transistor is turned on and the output suddenly decreases. If a signal having a pulse width from the starting point of the sweep of the ramp voltage to the sudden lowering point of the output is generated, the pulse width depends on the amount of the incident light. With the signal readout of this PWM method, it is possible to lower the power consumption while a wide dynamic range is maintained, and to downsize the picture cells to achieve a higher number of picture cells.

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patent: A 2005-198149 (2005-07-01), None
Shouho et al., “A Low-Voltage Pulse-Width-Modulation Image Sensor”, CCD & AIS, Jun. 9, 2005.

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