Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit
Reexamination Certificate
2001-03-06
2002-12-24
Pyo, Kevin (Department: 2878)
Radiant energy
Photocells; circuits and apparatus
Photocell controlled circuit
C250S2140LA, C348S308000
Reexamination Certificate
active
06498332
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a solid-state image sensing device for sensing an input one- or two-dimensional optical image.
2. Related Background Art
Image sensing devices using solid-state image sensing elements represented by a charge-coupled device (CCD) are used in various fields including home video cameras. However, when a CCD is used as an image sensing element having a relatively large light-receiving area, charges cannot be sufficiently transferred because of the low charge transfer efficiency of the CCD. Hence, of solid-state image sensing devices, MOS image sensors are used in specific fields because they have no problem of charge transfer efficiency.
A MOS image sensor for sensing a one- or two-dimensional optical image conventionally employs a scheme in which one discrete amplifier is arranged for a one- or two-dimensional photodiode array, and a photodetection signal from each photodiode is amplified and then extracted. In recent years, there is proposed an optical sensor device which maintains a linear photoelectric conversion characteristic even in an area with a small light amount in a short read time while exploiting the advantages of the MOS image sensor.
In this device, the output from a photodiode is read through a charge amplification circuit and source follower circuit (“Japanese Patent Laid-Open No. 5-215602 (prior art 1)”, and “J. C. Stanton, IEEE Transactions on Nuclear Science, Vol. 36, No 1, February 1989, pp. 522-527 (prior art 2)”.
FIG. 4
is a circuit diagram of a device disclosed in prior art 1. A device disclosed in prior art 2 also substantially has the same circuit arrangement as that of prior art 1. As shown in
FIG. 4
, the device comprises (a) sensors
930
1
to
930
N
each having a photodiode
910
and charge amplification circuit
920
for receiving a photodetection signal output from the photodiode
910
and integrating charges, and (b) a buffer circuit
970
having a clamp circuit
950
for receiving a signal output from a sensor
930
i
alternatively selected by a scanning circuit
940
and clamping the signal and a source follower circuit
960
for receiving the signal output from the clamp circuit
950
and generating a source follower output.
In this device, the charge amplification circuit
920
receives a current signal by charges generated in accordance with light incidence on the photodiode
910
and integrates the charges. An integration signal as a signal output from the sensor
930
i
alternatively selected in accordance with a scanning instruction signal output from the scanning circuit
940
is sequentially obtained through the clamp circuit
950
and then through the source follower circuit
960
.
SUMMARY OF THE INVENTION
In the above optical sensor device, when a two-dimensional image sensor or an image sensor having a one-dimensional array of photodiodes each paired with a signal processing circuit is formed, the following problems are posed.
(1) Problem of Linearity
In the device shown in
FIG. 4
, by the source follower circuit
960
of the MOSFET, the charge integration result output from the charge amplification circuit
920
is input from the gate of the MOSFET and output to an external circuit from the source of the MOSFET. Hence, letting VG be the gate potential, and VS be the source potential,
VS=VG−Vth
−(2
I/Kp
)
1/2
(1)
holds, where
Vth: threshold voltage of the MOSFET
I: drain current of the MOSFET
Kp: Constant based on manufacturing parameters and size of the MOSFET
The value Vth varies depending on the source potential VS. Hence,
Vth=Vth
0+&ggr;((
VS+Vb
)
1/2
−Vb
1/2
) (2)
where
Vth0: threshold voltage unique to the MOSFET
&ggr;: substrate constant unique to the MOSFET
Vb: base potential of the MOSFET
The base potential Vb is generally fixed to a predetermined potential by, e.g., grounding it for an NMOS.
As is apparent from equations (1) and (2), it is difficult to maintain a linear relationship between the gate potential VG, i.e., integration result signal and the source potential VS, i.e., output signal.
To prevent this, when interconnection is done such that the well potential of the MOSFET becomes the source potential VS, the parasitic capacitance largely increases due to the well, resulting in difficulty in high-speed operation.
(2) Problem of Operation Speed
In the device shown in
FIG. 4
, when the sensor
930
i
is selected by the scanning circuit
940
, the parasitic capacitance of the source terminal is immediately charged up to obtain the source potential VS shown in equation (1). To increase the charge-up speed of the parasitic capacitance of the source terminal for a high-speed operation, the value of steady-state current flowing to the source follower circuit must be increased.
However, when the value of steady-state current is increased, the voltage value between the gate and the source in the source follower circuit increases. As a result, the dynamic range of the output signal voltage narrows.
If the MOSFET size is increased to solve the above problem, the parasitic capacitance also increases, resulting in difficulty in high-speed operation.
That is, the device shown in
FIG. 4
cannot simultaneously realize high-speed operation and ensure the dynamic range of the output. This problem especially becomes serious when the constituent elements are integrated as an array.
The present invention has been made in consideration of the above situation, and has as its object to provide a solid-state image sensing device which enables high-speed operation while sufficiently ensuring the dynamic range of the output signal and reduces power consumption even when the elements are integrated.
In order to achieve the above object, according to the present invention, there is provided a solid-state image sensing device for sensing an input optical image, characterized by comprising (1) a light-receiving section in which the first number of light-receiving elements are arrayed along a first direction, each light-receiving element including a photoelectric conversion element for converting an input optical signal into a current signal and a switch element having a first terminal connected to a signal output terminal of the photoelectric conversion element and a second terminal for outputting the current signal generated by the photoelectric conversion element in accordance with a vertical scanning signal, and the second number of vertical light-receiving sections each having a signal output terminal electrically connected to the second terminals of the switch elements of the respective light-receiving elements are arrayed along a second direction, (2) the second number of integration circuits each for individually receiving an output from a corresponding one of the vertical light-receiving sections and performing an integration or non-integration operation of the current signal output from the vertical light-receiving section in a first capacitive element connected between an input and output terminals in accordance with a reset instruction signal, (3) the second number of sample-and-hold circuits each for receiving the signal output from a corresponding one of the integration circuits and performing a charge sample operation or charge hold operation for a second capacitive element in accordance with a sample instruction signal, (4) the second number of drive circuits each for receiving the signal output from a corresponding one of the sample-and-hold circuits and controlling an output drive ability in accordance with a horizontal scanning signal, (5) the second number of horizontal read circuits each for receiving the signal output from a corresponding one of the drive circuits and selectively outputting the signal in accordance with the horizontal scanning signal, and (6) a timing control section for issuing the vertical scanning signal, reset instruction signal, sample instruction signal, and horizontal scanning signal, wherein (7) the drive circuit comprises a differential amplifie
Hamamatsu Photonics K.K.
Morgan & Lewis & Bockius, LLP
Pyo Kevin
Sohn Seung C.
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