Solid state image pickup device and its read method

Details Solid state image pickup device and its read method Solid state image pickup device and its read method

2000-07-31

2004-11-23

Christensen, Andrew (Department: 2615)

Television

Camera, system and detail

Solid-state image sensor

C348S319000, C348S220100, C250S208100

Reexamination Certificate

active

06822682

ABSTRACT:

This application is based on Japanese Patent Applications HEI 11-231999 and HEI 11-232000 filed on Aug. 18, 1999, all the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a solid state image pickup device, and more particularly to a solid state image pickup device whose adjacent pixels are disposed shifted by a half pitch between pixels in both vertical and horizontal directions, and to its read method.
b) Description of the Related Art
High integration of pixels has been desired for a solid state image pickup device such as a CCD solid state image pickup device.
FIG. 18
is a plan view of a general interline type CCD solid state image pickup device.
The solid state image pickup device is formed on a semiconductor substrate
201
made of, for example, silicon.
A CCD solid state image pickup device X formed on the semiconductor substrate
201
includes pixels
203
, vertical charge transfer paths
205
, a horizontal charge transfer path
207
and an output amplifier
211
. A plurality of pixels
203
are regularly disposed on the semiconductor substrate
201
in the vertical and horizontal directions.
Each pixel
203
includes a photodiode (photoelectrical conversion element)
203
a
and a read gate (transfer gate)
203
b
. The photodiode
203
a
converts incident light into electric charges and stores the electric charges. The transfer gate
203
b
reads the electric charges stored in the photodiode
203
a
to the vertical charge transfer path
205
.
Each pixel column P
11
constituted of a plurality of pixels
203
disposed in the vertical direction is provided with one vertical charge transfer path
205
. The vertical charge transfer path
205
is made of, for example, an n-type conductive layer formed on the semiconductor substrate
201
. The horizontal charge transfer path
207
is disposed at the lower ends of the vertical charge transfer paths
205
.
The horizontal charge transfer path
207
is constituted of mainly an n-type conductive layer
208
in the semiconductor substrate
201
and horizontal charge transfer electrodes
221
made of two polysilicon layers (first and second polysilicon layers) formed on the semiconductor substrate
201
.
The n-type conductive layer
208
includes high concentration regions
208
a
having a high n-type impurity concentration and low concentration regions
208
b
having a low n-type impurity concentration formed alternately. The high concentration region
208
a
forms a potential well having a low potential energy. The low concentration region
208
b
forms a potential barrier having a high potential energy. Potential barriers and potential wells are alternately disposed in the horizontal direction. Two pairs of one potential barrier and one potential well form one charge transfer packet (hereinafter simply called a “packet”). A number of packets are formed along the horizontal direction.
First polysilicon layer electrodes (horizontal transfer electrodes
221
-
1
,
221
-
3
,
221
-
5
, . . . , refer to
FIG. 19
) are formed on the high concentration regions
208
a
(potential wells), and second polysilicon layer electrodes (horizontal transfer electrodes
221
-
0
,
221
-
2
,
221
-
4
, . . . , refer to
FIG. 19
) are formed on the low concentration regions
208
b
(potential barriers).
The horizontal charge transfer electrodes
221
-
0
and
221
-
1
are connected together and a voltage &phgr;
1
is applied to these electrodes. The horizontal charge transfer electrodes
221
-
2
and
221
-
3
are connected together and a voltage &phgr;
2
is applied to these electrodes. Similarly, the horizontal charge transfer electrode
221
-
4
and
221
-
5
are connected together and the voltage &phgr;
1
is applied to these electrodes.
As shown in
FIG. 19
, two vertical charge transfer electrodes
215
, e.g., vertical charge transfer electrodes
215
-
1
and
215
-
2
, are formed on the vertical charge transfer path
205
in a space between adjacent pixels disposed in the row direction.
Voltages V
1
to V
4
are applied to the vertical charge transfer electrodes
215
-
1
,
215
-
2
,
215
-
3
and
215
-
4
. Similarly the voltages V
1
to V
4
are applied to the vertical charge transfer electrodes
215
-
5
to
215
-
8
, and
215
-
9
to
215
-
12
. The voltages V
1
to V
4
are, for example, 0 V for forming a potential barrier in the vertical charge transfer path, 8 V for forming a charge transfer potential well, and 15 V for reading electric charges from pixels.
The vertical charge transfer path
205
is electrically connected to one potential well region of each packet of the horizontal charge transfer path
207
.
The operation of the solid state image pickup device will be described with reference to
FIGS. 18 and 19
.
When V
1
is set to 15 V, electric charges stored in all the photodiodes
203
a
connected to the V
1
vertical charge transfer electrodes are read via the transfer gates
203
b
to the vertical charge transfer paths
205
.
A relatively low plus voltage, e.g., 8 V, is applied to the vertical charge transfer electrode
215
-
1
, and also to the vertical charge transfer electrodes
215
-
2
and
215
-
3
. Then, the voltage at the vertical charge transfer electrode
215
-
1
is reset to 0 V and a voltage of 8 V is applied to the vertical charge transfer electrode
215
-
4
. These operations are repeated to transfer electric charges in the vertical charge transfer path
205
toward the horizontal charge transfer path by a four-phase driving method.
As a relatively low plus voltage, e.g., 8 V, is used as V
1
, V
2
nd V
3
, and 0 V is used as V
4
, the read electric charges distribute under three vertical charge transfer electrodes at V
1
, V
2
and V
3
.
As V
1
is reset to 0 V, the electric charges are confined under the electrodes at V
2
and V
3
. As V
4
is set to 8 V, the electric charges distribute under the electrodes at V
2
, V
3
and V
4
. By repeating this operation, the electric charges are transferred in the vertical charge transfer path
205
toward the horizontal charge transfer path by the four-phase driving method.
As the voltage &phgr;
1
of the horizontal charge transfer path is set, for example, to 0 V and the voltage &phgr;
2
to 8 V, electric charges under the &phgr;
1
electrode are transferred to the region under the right side &phgr;
2
electrode. At this time, a potential barrier is formed in the left region of the region under the &phgr;
1
electrode to prevent a counterflow of the electric charges.
Electric charges can therefore be transferred in the horizontal charge transfer path
207
by a two-phase driving method without a mixture of pixels.
With the two-phase driving method using the voltages &phgr;
1
and &phgr;
2
, electric charges can be transferred in the horizontal charge transfer path
207
.
With the above operations, electric charges can be read from pixels of each line connected to the V
1
vertical charge transfer electrode.
Next, electric charges are read from pixels on other rows by a similar method. After electric charges of all pixels for V
1
are read, a read pulse is used as V
2
to read electric charges from pixels connected to the V
2
vertical charge transfer electrodes. Similarly, electric charges are sequentially read from pixels connected to the V
3
and V
4
vertical charge transfer electrodes.
Electric charges transferred to the horizontal charge transfer path
207
are transferred to the output amplifier
211
, for example, by the two-phase driving method. The output amplifier
211
amplifies the electric charges and outputs image signals to the external.
By disposing photodiodes
203
a
two-dimensionally, signals of a two-dimensional image can be obtained.
In order to meet the requirements of high integration of pixels, it is necessary to make the pixel size fine.
With the solid state image pickup device X described above, one vertical charge transfer path
205
is provided for each pixel column P
11
. Four horizontal charge transfer electrodes
208
a
,
208
b
,
208
a
and
208

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