Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
2001-08-17
2003-01-28
Ngo, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S236000, C257S239000, C257S240000, C257S250000
Reexamination Certificate
active
06512254
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a solid-state image pickup device having a transfer register with an overflow drain.
2. Description of the Related Art
According to a conventional technique, when overflow control is carried out in a transfer register of a CCD solid-state image pickup device, an overflow barrier is formed at the side of a polycrystal silicon layer serving as a lower layer constituting a storage electrode of the transfer register by a polycrystal silicon layer serving as an upper layer and an implant for a barrier.
FIG. 5
is a schematic diagram (plan view) showing a conventional overflow controlling structure.
As shown in
FIG. 5
, first-layer transfer electrodes
51
and second-layer transfer electrodes
52
are alternately arranged on a transfer register
50
. The first-layer transfer electrodes
51
serve as storage electrodes St
1
, St
2
, and the second-layer transfer electrodes
52
serve as transfer electrodes Tr
1
, Tr
2
.
A first-phase driving pulse &phgr;
1
is applied as driving pulses &phgr;St
1
, &phgr;Tr
1
to the storage electrode St
1
and the transfer electrode Tr
1
respectively, and a second-phase driving pulse &phgr;
2
is applied as driving pulses &phgr;St
2
, &phgr;Tr
2
to the storage electrode St
2
and the transfer electrode Tr
2
, respectively. Further, an overflow control gate OFCG and an overflow drain OFD are provided at the side of the first-phase storage electrode St
1
disposed substantially at the center of FIG.
5
.
FIG. 6
is a cross-sectional view taken along Y-Y′ of FIG.
5
.
As shown in
FIGS. 5 and 6
, the overflow control gate OFCG comprises a gate electrode
54
and an N
−
area
56
. The gate electrode
54
is formed of the same second-layer polycrystal silicon layer as the second-layer transfer electrodes
52
constructing the transfer electrodes Tr
1
, Tr
2
. A driving pulse &phgr;OFCG is applied to the gate electrode
54
.
In the N
−
area
56
, N-type impurities are ion-implanted into a P-type well region
2
of a semiconductor substrate
1
.
The overflow drain OFD is constructed by an N
++
area
55
which is formed by ion-implanting high-concentration N-type impurities into the P-type well region
2
of the semiconductor substrate
1
. In
FIG. 5
, reference numeral
3
represents an N
+
area formed below the storage electrodes St
1
, St
2
, and charges under transfer are accumulated in the area
3
.
FIG. 7
is a potential diagram along Y-Y′ of FIG.
5
.
As shown in
FIG. 7
, the overflow control gate OFCG based on the gate electrode
54
and the N
−
area
56
serves as a barrier, and charges flowing over the barrier are discarded to the overflow drain OFD.
With this construction, factors affecting the height of the barrier of the overflow control gate OFCG are the length of a portion of the gate electrode
54
of the overflow control gate OFCG that is not overlapped with the first-phase storage electrode St
1
, that is, the effective length of the overflow control gate OFCG, and the concentration of the impurities in the N
−
area
56
, etc.
FIG. 8
is a timing chart showing the driving pulses in the construction of FIG.
5
.
The driving pulse &phgr;St
1
of the first-phase storage electrode ST
1
and the driving pulse &phgr;Tr
1
of the first-phase transfer electrode Tr
1
are commonly applied by the same driving pulse (first-phase driving pulse &phgr;
1
), and the driving pulse &phgr;St
2
of the second-phase storage electrode ST
2
and the driving pulse &phgr; Tr
2
of the second-phase transfer electrode Tr
2
are commonly applied by the same driving pulse (second-phase driving pulse &phgr;
2
). The first-phase driving pulse and the second-phase driving pulse &phgr;
2
are opposite to each other in phase. The driving pulse &phgr; OFCG of the overflow control gate OFCG has the same phase as the first-phase driving pulse &phgr;
1
.
With this setting, the following charge transfer and overflow operation is carried out.
When the first-phase driving pulse &phgr;
1
is in high level Hi and charges exist in the first-phase storage electrode St
1
, the driving pulse &phgr; OFCG of the overflow control gate OFCG is also in high level Hi and thus the overflow barrier is low in height, so that overflow can be induced with a predetermined amount of charges.
On the other hand, when the first-phase driving pulse &phgr;
1
is in low level Lo and charges are transferred from the first-phase storage electrode St
1
to the adjacent second-phase electrodes Tr
2
, St
2
, the driving pulse &phgr; OFCG of the overflow control gate OFCG is also in low level Lo and thus the overflow barrier is high in height, so that the charges under transfer can be prevented from flowing over the barrier.
However, in the case of the above conventional technique, if a positional displacement occurs between the first-phase storage electrode St
1
formed of the first-layer polycrystal silicon layer serving as the lower layer and the gate electrode
54
of the overflow control gate OFCG formed of the second-layer polycrystal silicon layer serving as the upper layer, the effective length L
1
of the overflow control gate OFCG would vary.
If the effective length L
1
varies, the height of the barrier based on the overflow control gate OFCG is also varied. Further, the relationship between the effective length L
1
and the effective length L of the transfer electrode Tr
1
which determines the height of the barrier of the transfer channel
50
is also varied.
In addition, the height of the barrier based on the overflow control gate OFCG is also varied due to the positional displacement between the N
−
area
56
and the gate electrode
54
, the dispersion in line width among the polycrystal silicon layer
51
serving as the lower layer and the polycrystal silicon layers
52
,
54
serving as the upper layer, etc.
When the dispersion such as the positional displacement or the like is large, the difference between the barrier height of the overflow control gate OFCG and the barrier height of the transfer electrode Tr
1
decreases or excessively increases, so that there occurs such a case that the overflow control cannot be properly performed. This problem obstructs the fine control and microstructuring design of solid-state image pickup devices.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a solid-state image pickup device for performing proper overflow control.
In order to attain the above object, there is provided a solid-state image pickup device in which a transfer register is provided with an overflow control gate and an overflow drain, and the gate electrode of the overflow control gate is formed so as to be superposed on the lower-layer electrodes of the transfer register side and the overflow drain side.
According to the solid-state image pickup device of the present invention, since the gate electrode of the overflow control gate is formed so as to be superposed on the lower-layer electrodes of the transfer register side and the overflow drain side, the effective length of the overflow control gate is determined by the interval between the lower-layer electrodes of the transfer register side and the overflow drain side.
REFERENCES:
patent: 4984045 (1991-01-01), Matsunaga
patent: 4993053 (1991-02-01), Itoh et al.
patent: 5539226 (1996-07-01), Kawamoto et al.
patent: 6310369 (2001-10-01), Narabu et al.
Kananen, Esq. Ronald P.
Ngo Ngan V.
Rader & Fishman & Grauer, PLLC
Sony Corporation
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