Solid-state image pickup device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device

Reexamination Certificate

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Details

C257S233000, C257S241000, C257S243000

Reexamination Certificate

active

06337495

ABSTRACT:

This application is based on Japanese Patent Applications HEI 11-161248 filed on Jun. 8, 1999 and 2000-165315 filed on Jun. 2, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a solid-state image pickup device using photodiodes.
b) Description of the Related Art
A schematic cross sectional view of a conventional solid-state image pickup device is shown in
FIG. 15
in its upper area.
A photodiode is made of a p-type semiconductor well region
51
and an n-type semiconductor region
54
(hereinafter called a “charge accumulation region
54
”) respectively formed on a principal surface of a semiconductor substrate, and a p
+
-type semiconductor region
55
(hereinafter called a “burying layer
55
”) formed on the surface of the charge accumulation region
54
. Formed in the p-type semiconductor well region
51
are an n-type semiconductor region
53
(hereinafter called a “charge transfer channel
53
”) for forming a charge transfer path and a p-type semiconductor region
52
(hereinafter called a “channel stopper region
52
”) for forming a channel stopper.
On the surface of the semiconductor substrate having these regions, an electrode
57
having a predetermined pattern is formed, with an insulating film
56
being interposed therebetween. The electrode
57
covers the upper area of a partial area (hereinafter called a “readout gate channel
51
a
”) of the p-type semiconductor well region
51
between the charge accumulation region
54
and charge transfer channel
53
.
The burying layer
55
covering the charge accumulation region
54
captures the centers of electron-hole pair generation recombination (GR) formed at the interface between the semiconductor substrate surface and insulating film
56
, and recombines electron-hole pairs generated in the GR centers. Generation of noises can therefore be suppressed. The burying layer
55
has also a function of increasing a pn junction area of the photodiode and improving the photosensitivity.
The left end of this burying layer
55
connects the channel stopper region
52
and the right end thereof connects the readout gate channel
51
a
. The connection area between the burying layer
55
and channel stopper region
52
is not only that shown in FIG.
15
. The burying layer
55
and channel stopper region
52
also connect together at the outer periphery of the charge accumulation region
54
as viewed in plan, excepting the area connected to the readout gate channel
51
a.
After the channel stopper region
52
, charge transfer channel
53
, charge accumulation region
54
and the like are formed, the burying layer
55
is formed by ion-implanting p-type impurities into the surface area of the charge accumulation region
54
to form a P
+
-type region and thereafter activating these p-type impurities by a heat treatment. This ion-implantation is performed by aligning an outer edge of an ion-implantation region with the channel stopper region
52
.
Another solid-state image pickup device is known which has a similar structure as that shown in
FIG. 15
excepting that the right end of the burying layer
55
is slightly spaced apart from the readout gate channel
51
a.
The middle area of
FIG. 15
shows a potential P
1
relative to electrons near the surface of the semiconductor substrate when 0 V is applied to the electrode
57
.
In this specification, the region having a deeper potential well while a voltage is applied is called as “the region has a higher potential”, and the region having a shallower potential well is called as “the region has a lower potential”.
The channel stopper region
52
is at the ground potential. The potentials at the charge accumulation region
54
and charge transfer channel
53
are higher than the potential at the channel stopper region
52
. The potential at the readout gate channel
51
a
is lower than the potentials at the charge accumulation region
54
and charge transfer channel
53
.
As light becomes incident upon the photodiode, the photodiode absorbs incidence light and generates electric charge. The charge accumulation region
54
accumulates electric charge (electrons) Q corresponding to a quantity of light. The photodiode corresponds to a pixel, and the accumulated charge Q corresponds to a pixel signal.
The readout gate channel
51
a prevents the charge Q from moving from the photodiode to the change transfer channel
53
. Namely, the readout gate channel
51
a
forms a potential barrier.
The lower area of
FIG. 15
shows a potential P
2
relative to electrons near the surface of the semiconductor substrate while a readout pulse is applied to the electrode
57
to transfer electric charge accumulated in the photodiode to the charge transfer channel
53
. The channel stopper region
52
is at the ground potential also in this case.
As the readout pulse of, for example, 15V is applied to the electrode
57
, the electron potential at the semiconductor region under the electrode
57
becomes high. Since the potential at the readout gate channel
51
a
becomes high, the function as the potential barrier is degraded. Electric charge Q in the charge accumulation region
54
flows into the charge transfer channel
53
. At the readout pulse of about 15V, a low potential barrier may remain at the readout gate channel
51
a.
If such a potential barrier is left at the readout gate channel
51
a
, only some electric charge Q
2
of the electric charge Q is transferred to the charge transfer channel
53
, and some other electric charge Q
1
is left in the charge accumulation region
54
. The electric charge Q
1
appears as noise on an image. This noise is retained image noise. Noises different from retained image noise are also generated.
Retained image noise can be reduced if the potential of the readout pulse is raised. The potential barrier formed in the readout gate channel
51
a
can be lowered if the right end of the burying layer
55
is slightly spaced apart from the readout gate channel
51
a
even if the potential of the readout pulse is set to, for example, 15 V.
Even if the right end of the burying layer
55
is slightly spaced apart from the readout gate channel
51
a
, it is difficult to suppress generation of noises other than retained image noise.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a solid-state image pickup device capable of suppressing generation of noises.
According to one aspect of the present invention, there is provided a solid state image pickup device comprising: a semiconductor substrate formed with a semiconductor well region on a principal surface side; a charge accumulation region column having a plurality of charge accumulation regions formed in the semiconductor well region, each of the charge accumulation regions having a conductivity type opposite to a conductivity type of the semiconductor well region; a charge transfer channel formed in the semiconductor well region adjacent to said charge accumulation region column and extending along said charge accumulation region column, said charge transfer channel having the conductivity type opposite to the conductivity type of the semiconductor well region; a readout gate channel formed in the semiconductor well region for each charge accumulation region, said readout gate channel having a conductivity type same as the conductivity type of the semiconductor well region and being contiguous to a corresponding charge accumulation region and said charge transfer channel; a channel stopper region formed in the semiconductor well region and extending at least along said charge accumulation region column on an opposite side of said charge transfer channel relative to a center line of said charge accumulation region column, said channel stopper region having the conductivity type same as the conductivity type of the semiconductor well region and an impurity concentration higher than an impurity concentration of the semiconductor well region; and a burying layer formed

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