Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
1998-10-22
2001-08-28
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S292000
Reexamination Certificate
active
06281531
ABSTRACT:
FIELD OF THE INVENTION
This invention pertains to a solid picture element and methods of manufacture of the solid picture element. More particularly, this invention pertains to the structure of a light receiving part of the solid picture element and its methods of manufacture.
BACKGROUND OF THE INVENTION
A solid-state image sensing device, such as a charge-coupled device, responds to incident light to generate signal charges that are stored in a depletion region and produce an output signal at an output terminal thereof. A basic charge-coupled device includes a metal-oxide semiconductor device in which a metal electrode is positioned on, and insulated from, a silicon substrate. Charge-coupled devices, or solid picture elements, are arranged in arrays and coupled to circuitry that samples the devices for use in, for example, generating a video image.
In recent years, to increase the sensitivity of picture elements, several types of elements known as amplifier type picture elements have been disclosed in which a transistor for amplifying signals is installed. An example of this is disclosed by Japanese unexamined patent application no. 8-293591. The elements disclosed by this patent application are several examples in which a charge accumulation portion that accumulates charges produced in response to light incident on a light receiving part and an amplifying transistor that outputs signals in response to charges detected are formed in separate locations, and a transfer gate is installed between these to control the transfer of charges from the charge accumulation portion to the amplifying transistor. Of these, examples are disclosed in which the photodiode of the light receiving part is a buried photodiode (BPD), and in which the amplifying transistor is a junction field effect transistor (JFET).
FIG. 13
shows a schematic plan of a unit pixel of a prior art solid picture element. In addition,
FIG. 18
shows an example of an overall circuit structure of a solid picture element.
The prior art solid picture element, shown in
FIG. 13
, is comprised of parts that include BPD
301
that is a light receiving part or photoelectric converter part, JFET
302
that amplifies the photoelectrically converted charge, transfer gate
303
that controls transfer of charges from BPD
301
to JFET
302
, reset drain
304
that applies a reset potential to the JFET gate, and reset gate
305
that controls the JFET reset operation.
FIG. 14
is a cross section of the solid picture element shown in
FIG. 13
taken along line X-X′.
As shown in
FIG. 14
, N-type well
202
is formed in P-type substrate
201
. Formed in this N-type well
202
are BPD P-type charge accumulation layer
203
and N-type depletion prevention layer
204
, P-type gate
205
used as the JFET gate on the substrate surface, N-type channel
206
used as the JFET channel, deep P-type gate
207
used as the JFET gate below the channel, N-type source
208
used as the JFET source, and N-type drain
209
used as the JFET drain and as an element separator.
Because normally each of these regions is formed by implanting ions selectively into the surface of semiconductor substrate
201
, then heating and diffusing the substrate, the impurity concentration becomes lower the deeper the layer is in the semiconductor substrate, and the impurity concentration also is reduced gradually by horizontal diffusion in the region close to the edge of masks during ion implantation. Transfer gate
210
, which is an electrode that controls transfer of charges on the surface of substrate
201
from the BPD to the JFET, is installed on an insulating film (not shown in the figure), such as silicon oxide film. In addition, connecting parts (not shown) connect P-type gate
205
to deep P-type gate
207
, and N-type well
202
to N-type depletion prevention layer
204
to maintain gate
205
and deep gate
207
, and well
202
and layer
204
, at the same potential. Furthermore,
FIG. 14
does not show an aluminum, or similar, pattern that is connected to JFET N-type source
208
.
Generally, prior art solid picture elements or the type of
FIG. 14
are fabricated by a method such as shown schematically in
FIGS. 17
a
-
17
c
.
FIGS. 17
a
-
17
c
do not show regions corresponding to JFET
302
, reset drain
304
, and rest gate
305
in FIG.
14
.
With reference to
FIGS. 17
a
-
17
c
, N-type well
202
is formed in P-type semiconductor substrate
201
, and a protective oxide film
214
, a relatively thin insulating film, is formed on the surface of substrate
201
either before or after forming N-type well
202
. Resist mask
215
is formed on the protective oxide film
214
on the surface of substrate
201
. By implanting P-type ions
221
near the surface of substrate
201
, and using resist mask
215
as a mask, then heating and diffusing the substrate, BPD P-type charge accumulation layer
203
is formed in N-type well
202
(FIG.
17
(
a
)).
By implanting N-type ions
222
near the surface of substrate
201
using the same resist mask
215
as a mask, then heating and diffusing the substrate, N-type depletion prevention layer
204
is formed in P-type charge accumulation layer
203
(FIG.
17
(
b
)). P-type charge accumulation layer
203
and N-type depletion prevention layer
204
also can be formed by heat diffusion by implanting P-type ions
221
and implanting N-type ions
222
, then performing heat treatment all at once.
Resist mask
215
is then removed, gate oxide film
213
is formed on the surface of substrate
201
(e.g., by making the thickness of protective oxide film
214
thicker) and transfer gate
210
is formed of a material such as polysilicon on gate oxide film
213
(FIG.
17
(
c
)).
P-type charge accumulation layer
203
and N-type depletion prevention layer
204
also can be formed by implanting P-type ions or N-type ions without using resist mask
215
by using at least part of transfer gate
210
as a mask. But, in either case, the edge of the mask when used to implant ions to form P-type charge accumulation layer
203
is either in the same position as, or closer to, the JFET than the edge of the mask when used to implant ions to form N-type depletion prevention layer
204
.
Next, the prior art charge transfer operation, from P-type charge accumulation layer
203
to the JFET in this type of solid picture element, is explained.
As an example, substrate potential is set to 0 V and N-type well
202
and N-type depletion prevention layer
204
are set to 5 V When a charge has accumulated on the BPD, transfer gate
210
is set to 5 V and placed in OFF state. In addition, by setting reset gate
305
to an ON state by applying a voltage and setting reset drain
304
to −5 V, the JFET P-type gate becomes the same −5 V as the potential of reset drain
304
, and the JFET is placed in an OFF state. Because the part of P-type charge accumulation layer
203
that contacts the surface of semiconductor substrate
201
is inverted to N-type at this time, the speed of generation of noise current in this part is slow. Charge accumulates in BPD P-type charge accumulation layer
203
and the potential of P-type charge accumulation layer
203
rises, and when this reaches a certain level of potential or higher, the charge overflows into the substrate.
When a charge is transferred from the BPD to the JFET, first, by placing reset gate
305
in an ON state and setting reset drain
304
to −2 V, the JFET P-type gate
205
is set to −2 V. Next, by placing reset gate
305
in an OFF state, the JFET P-type gate
205
becomes floating. Next, transfer gate
210
is set to −2 V and placed in ON state, and the charge is transferred from BPD P-type charge accumulation layer
203
to JFET P-type gate
205
.
As charges are transferred to P-type gate
205
and deep P-type gate
207
, the potential of P-type charge accumulation layer
203
drops and the potential of JFET P-type gate
205
and deep P-type gate
207
rises. When the potential of JFET N-type source
208
is set, for example, to approximately 0 V by a read circuit
Kamashita Atsushi
Suzuki Satoshi
Ipsolon LLP
Munson Gene M.
Nikon Corporation
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