Solid image pickup apparatus

Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Electromagnetic or particle radiation

Reexamination Certificate

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Details

C257S431000

Reexamination Certificate

active

06727564

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a solid image pickup apparatus having a solid image pickup element and an optical lens disposed on a flexible printed circuit board.
BACKGROUND OF THE INVENTION
FIG. 10
shows a conventional solid image pickup apparatus. This solid image pickup apparatus comprises a solid image pickup element and an optical lens, with the solid image pickup element and an integrated circuit (IC) chip connected to a flexible printed circuit board. The reference numeral
1
denotes the flexible printed circuit board (FPC),
1
a
denotes an FPC lead section, and
2
b
denotes a reinforcing plate. The reference numeral
3
denotes a terminal provided on the flexible printed circuit board
1
for connecting the board to some other device,
4
denotes a fixed pedestal,
5
denotes a fixed cap,
13
denotes a casing, and
8
denotes a diaphragm.
FIG. 9
shows a cross-sectional view of the solid image pickup apparatus shown in FIG.
10
. The fixed pedestal
4
is fixed to the FPC
1
via the reinforcing plate
2
b
while holding the optical filter
7
. The fixed cap
5
is installed on the fixed pedestal
4
in a movable status for adjusting the diaphragm of the optical lens
6
while holding the optical lens
6
. The fixed pedestal
4
and the fixed cap
5
constitute the casing
13
that holds the optical lens
6
and the optical filter
7
. A solid image pickup element
9
is connected to the wiring of the FPC
1
via a flip-chip electrode connecting section
11
. An IC
10
that performs image signal processing is connected to the wiring of the FPC
1
via the flip-chip electrode connecting section
11
. A reinforcing plate
2
a
is adhered to the rear surface of the FPC
1
on the front surface of which the IC
10
is installed. A chip
12
, such as a capacitor, is connected to the wiring of the FPC
1
. The reference numeral
14
denotes an opening section of the FPC
1
.
The operation of the solid image pickup apparatus shown in FIG.
9
and
FIG. 10
will be explained next. Light that has entered the diaphragm section
8
passes through the optical lens. The light further passes through the optical filter
7
, and irradiates an image pickup area of the solid image pickup element
9
, thereby to form an image in this area. The information about this image is converted into an electric signal. This electric signal (“image pickup signal”) is sent to the FPC
1
via the flip-chip electrode connecting section
11
of the solid image pickup element
9
. Finally, the image pickup signal is sent to the IC
10
via the wiring of the FPC
1
and via the flip-chip electrode connecting section
11
of the IC
10
. The electric signal is processed and sent back to the FPC
1
via the flip-chip electrode connecting section
11
. The image pickup electric signal is taken out from the terminal
3
via the FPC lead section
1
a
of the FPC
1
.
Usually, a large-scale integrated device (LSI) of a complementary metal-oxide semiconductor (CMOS) structure is mostly used for the solid image pickup element
9
and the IC
10
. According to the LSI of the CMOS structure, when a metal-oxide semiconductor (MOS) transistor that constitutes the circuit has been switched on, a through current flows from a power source line to a ground line. This through current becomes a noise source, and noise passes through the power source inside the LSI and the ground wiring. This noise propagates in superimposition with the power source voltage, and appears between the power source terminal and the ground terminal of the LSI. The CMOS through current brings about mutual interference as noise between circuits inside the solid image pickup element
9
, between circuits inside the IC
10
, and between the solid image pickup element
9
and the IC
10
, respectively. As a result, there occurs a phenomenon that the image pickup electric signal is degraded. Further, the noise also becomes a cause of an erroneous operation of other devices as EMI (Electromagnetic Interference).
Particularly when the LSI of the CMOS structure is used for the solid image pickup element
9
, it is necessary to achieve further progress in fine processing in the LSI manufacturing to meet demand for increase in the number of pixels and demand for high image quality, along with a reduction in pixel sizes. Further, when the LSI of the CMOS structure is used for the IC
10
, it is necessary to promote fine processing in the LSI manufacturing to further improve functions, reduce LSI chip sizes, lower costs, and increase the speed of circuit operation, along with the increase in circuit density. When fine processing in the LSI manufacturing progresses, the withstand voltage of the MOS transistor inevitably becomes low. Therefore, it becomes necessary to lower the power source voltage. This reduces the margin for restricting noise of the circuits. The reduction in the noise restriction margin becomes the cause of an erroneous operation due to noise from other devices as EMS (Electromagnetic Susceptibility).
In order to improve the speed of the circuit operation inside the LSI, there been an attempt to lower the resistance between the source and the drain of the CMOS transistors and carry out fast charging and discharging of the gate capacitance in the next-stage circuit. This shortens the rise time and the fall time of the through current in the switching operation. Further, a high-frequency component of the through current that flows from the power source line to the ground line increases, resulting in an increase in noise attributable to the through current.
In order to reduce the degrading of the image pickup electric signal due to the noise attributable to the through current, there has been made the following attempt. A capacitor is connected between the power source terminal and the ground terminal of each of the solid image pickup element
9
and the IC
10
. The noise is bypassed through the capacitor, thereby to reduce the noise interference between the circuits inside the LSI, and reduce the noise interference between the solid image pickup element
9
and the IC
10
. In order to minimize the sizes of the solid image pickup element, the chip
12
is usually used for these capacitors.
As the conventional solid image pickup apparatus has the above structure, a capacitor using the chip
12
is connected to the power source line of the solid image pickup element
9
and the IC
10
respectively in order to reduce the noise. The capacitor using the chip
12
is connected to a connection land and formed on the FPC
1
by soldering. Therefore, it is necessary to prevent other connection lands from being polluted due to the flying of the soldering flux and the flow of the solder wax on the wiring of the FPC
1
at the soldering time. Consequently, it has been necessary to set at least a predetermined distance (for example, a few mm) between the solid image pickup element
9
and the chip
12
, and between the IC
10
and the chip
12
, respectively.
In order to prevent the pollution of the connection land of the solid image pickup element
9
and the connection land of the IC
10
respectively due to the flying of flux and the flow of solder wax at the soldering time, it has been necessary to apply a provisional sealing to cover these connection lands before starting the soldering operation. After completing the soldering, the provisional sealing is removed, thereby to prevent the lands from being polluted. As space for applying the provisional sealing is necessary, it has been necessary to secure at least a predetermined distance (for example, a few mm) between the solid image pickup element
9
and the chip
12
and between the IC
10
and the chip
12
respectively on the FPC
1
.
In order to prevent the fitting tool from colliding against the chip
12
at the time of fitting the solid image pickup element
9
and the IC
10
on the FPC
1
, it has been necessary to secure a distance (for example, a few mm) between the solid image pickup element
9
and the chip
12
and between the IC
10
and the chip
12
respe

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