Solderless test interface for a semiconductor device package

Details Solderless test interface for a semiconductor device package Solderless test interface for a semiconductor device package

2002-12-27

2004-11-23

Stoner, Kiley (Department: 1725)

Metal fusion bonding

Process

With measuring, testing, indicating, inspecting, or...

C228S104000, C324S500000, C324S537000

Reexamination Certificate

active

06820794

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a solderless test interface for a semiconductor device package, and, more particularly, to a temporary, very low electrical resistance, connection between the external contacts of a semiconductor device package and the conductive pads of a test board which permits accurate testing of the package.
BACKGROUND OF THE INVENTION
Numerous types and styles of semiconductor products are known wherein various semiconductor devices, integrated circuits and other miniature electrical items are electrically and physically associated in a package having external electrical contacts that are electrically continuous with the devices and circuits within the package. The external contacts permit the electrical connection of the package to a printed circuit (or wiring) board (“PCB”) carrying other such packages or circuitry and other electrical devices to yield an operative utilization device, such as television chassis or an electrical assembly such as a computer motherboard. The popularity of small portable devices, such as audio players, personal information managers and cellular telephones, has required the design of new highly miniaturized package designs with high numbers of electrical contacts arranged in very dense patterns to conserve physical space. These newer package designs present unique challenges for making external electrical connection for PCB assembly and in particular, for electrical testing of the semiconductor device.
Before a packaged semiconductor device is incorporated into its use environment, it must be electrically tested. Typically, testing is effected by engaging conductive pads on a test board—which are connected to test circuitry—with the external contacts of the package. This engagement may be direct or indirect. Indirect engagement may be achieved by inserting the device package into a test socket where package external contacts engage with socket terminals of which are then engaged with the test pads. In the foregoing test techniques, electrical resistance at the contact-pad interface—or at the contact-plug/terminal-pad interface when a test socket is used—impedes current flow through the Device-Under-Test (DUT) and the test circuitry. This contact resistance is not a problem in many test situations, but may significantly hinder or prevent accurate testing of packages through which relatively high test currents must flow.
Specifically, in testing semiconductor packages that include certain types of low dropout (“LDO”) regulators it has been found that the sum of the output impedance of a DUT and the contact resistance must be well below about 0.1 ohm. Electrical testing using indirect (test socket) engagement methods have been found to be unsatisfactory for testing LDOs as the relevant contact resistances cause the foregoing sum to far exceed 0.1 ohm which introduces measurement error of certain critical electrical parameters. Lowering of the contact resistance may be achieved by soldering the DUT's external contacts directly to the test board, but this requires soldering/de-soldering each DUT which quickly degrades the test board condition. Another method is to solder the DUT directly to a daughter board which then engages with the test board via a connector, but the contact resistance of the connector between such a board and the test board is unacceptably high. Either soldering method either consumes the package or necessitates costly de-soldering after test.
SUMMARY OF THE INVENTION
From the foregoing it may be seen that there exists a need for a technique that permits establishment of a very low electrical resistance connection between the external contacts of a semiconductor package and the conductive pads of a test board.
This need is abrogated by the present invention, which provides apparatus and methods for establishing a temporary low electrical resistance connection between the external contacts of a semiconductor device package and the conductive pads of a test board, so that contact-resistance-sensitive testing of LDOs and similarly sensitive devices may be accurately achieved.
The semiconductor device package may be a BGA, or ball grid array, package. The external contacts of a BGA package take the form of a pattern, grid or group of conductive balls on a surface of the package, although other external contacts are contemplated by the present invention.
The apparatus of the invention first comprises a thin, planar, flexible electrically insulative substrate. The substrate has formed therethrough a plurality of apertures. The pattern of the aperture termini or ends on one side of the substrate are congruent with the pattern of the package balls or other external contacts. As used herein, “congruent” means “coinciding when superimposed.” The pattern of the aperture termini or ends on the other side of the substrate are congruent with the pattern of the conductive pads. When the device package and the test board are opposed so that the external contacts and the conductive pads face each other, the substrate is insertable therebetween to align the respective termini groups simultaneously align with the external contacts and the pads.
The apparatus also includes an electrically continuous, thin coating of a highly conductive metal on the wall of each aperture and on both surfaces of the substrate surrounding both termini of each aperture. The metal may be copper that is plated on the wall of each aperture and that assumes an annular pattern surrounding each aperture terminus. Any technique generally referred to as “through-hole plating” may be utilized. Any other metal or alloy that is highly conductive and can be plated or otherwise expeditiously deposited onto the substrate material may also be used.
The apparatus finally includes a soft metal layer on the coating. The metal, which may be tin-lead, or soft “bondable” gold, may be deposited on the thin metal coating by plating or functionally similar techniques. The soft metal is of a type that experiences cold flow deformation when minimal force is applied thereto. Specifically, the force is applied to the soft metal surrounding the aperture termini on one surface of the substrate by the external contacts or balls and to the soft metal surrounding the aperture termini on the other surface of the substrate by the pads. This force application occurs as the package and the test board are urged together. The cold flow deformation effects a very low electrical resistance engagement between the balls and the soft metal, on one hand, and the pads and the soft metal, on the other hand. In this way a very low electrical resistance path between the balls and the pads is established through the soft-metal-coated highly conductive metal coating.
More specifically the deformation of the soft metal into intimate conformity with the balls and the pads, resulted in less than 0.020 Ohms of contact resistance being introduced into the test circuit. The force necessary to urge the package and the test board together to achieve this effect is nominal.
The diameter of the aperture termini after the soft metal is deposited is preferable smaller than the diameter of the balls so that the balls may be said to be slightly “nested” in the apertures.
Since no permanent bond is formed between the substrate and the package, following testing, the package is removed for further processing or shipment and further packages are tested. If the forces utilized are sufficiently low, a given substrate may be re-used. Typically, however, the substrates, which are relatively inexpensive, are discarded after a single use.
The test board may include two or more guide posts which are received by guide holes formed through the substrate. In this way the substrate applicable to a given ball and pad configuration may be aligned with the pads on the test board and with the balls of a package to be tested.
The method according to the present invention includes the method of making the apparatus and the method of using same. Both are believed to be sufficiently clear from the foregoin

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