Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,... – With provision to conduct electricity from panel circuit to...
Reexamination Certificate
2005-01-11
2005-01-11
Myers, Paul R. (Department: 2112)
Electrical connectors
Preformed panel circuit arrangement, e.g., pcb, icm, dip,...
With provision to conduct electricity from panel circuit to...
C439S091000, C361S768000
Reexamination Certificate
active
06840777
ABSTRACT:
To decrease the thickness, or stack height, of an electronics package, the package includes a solderless compression connector between an integrated circuit (IC) package and a substrate such as a printed circuit board (PCB). In one embodiment, the IC package is mounted on the substrate using a land grid array arrangement. Corresponding lands on the IC package and substrate are coupled using a solderless compression connector. The compression connector includes a plurality of electrically conductive elements, such as compressible button contacts, and an apertured support that aligns the button contacts with corresponding lands on the IC package and substrate. In another embodiment, the connector includes electrically conductive pins embedded in a thin plastic sheet. In a further embodiment, the connector includes a microcrystalline film having electrically conductive crystals. In a further embodiment, the compression connector is used within an IC package to couple an IC to an IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system, are also described.
REFERENCES:
patent: 4268956 (1981-05-01), Parks et al.
patent: 4355082 (1982-10-01), Bischoff et al.
patent: 4574331 (1986-03-01), Smolley
patent: 4581679 (1986-04-01), Smolley
patent: 4731693 (1988-03-01), Berg et al.
patent: 4813129 (1989-03-01), Karnezos
patent: 4924353 (1990-05-01), Patraw
patent: 4926549 (1990-05-01), Yoshizawa et al.
patent: 4954875 (1990-09-01), Clements
patent: 5109320 (1992-04-01), Bourdelaise et al.
patent: 5237203 (1993-08-01), Massaron
patent: 5281771 (1994-01-01), Swift et al.
patent: 5298686 (1994-03-01), Bourdelaise et al.
patent: 5329423 (1994-07-01), Scholz
patent: 5334029 (1994-08-01), Akkapeddi et al.
patent: 5434452 (1995-07-01), Higgins, III
patent: 5440454 (1995-08-01), Hashimoto et al.
patent: 5444301 (1995-08-01), Song et al.
patent: 5485351 (1996-01-01), Hopfer et al.
patent: 5701233 (1997-12-01), Carson et al.
patent: 5822197 (1998-10-01), Thuault
patent: 5860818 (1999-01-01), Sakaki et al.
patent: 5886413 (1999-03-01), Knott et al.
patent: 5886535 (1999-03-01), Budnaitis
patent: 5911583 (1999-06-01), Roybal et al.
patent: 5949654 (1999-09-01), Fukuoka
patent: 5953214 (1999-09-01), Dranchak et al.
patent: 5958590 (1999-09-01), Kang et al.
patent: 6064573 (2000-05-01), Morton
patent: 6078500 (2000-06-01), Beaman et al.
patent: 6225143 (2001-05-01), Rao et al.
patent: 6229209 (2001-05-01), Nakamura et al.
patent: 6247938 (2001-06-01), Rathburn
patent: 6323559 (2001-11-01), Chan et al.
patent: 6365421 (2002-04-01), Debenham et al.
patent: 6407929 (2002-06-01), Hale et al.
patent: 6617528 (2003-09-01), Armezzani et al.
patent: 406231818 (1994-08-01), None
patent: 407296868 (1995-11-01), None
patent: 411074051 (1999-03-01), None
patent: 411329541 (1999-11-01), None
patent: WO 8704009 (1987-07-01), None
Kuozkowski, “The Electrical Conductivity and Breakdown Phenomena in Polyester Polyer-Quinoline Salt of Tetracyanoquinodimethane Composites”, IEEE; pp. 158-162.*
Guarin et al., “Contact Resistance Degradation in Z-Axis Connectors Operated at Burn-In Temperatures”, IEEE 1993, pp. 892.*
Guarin et al., “Solderless High-Density Interconnects for Burn-In Applications”, IEEE 1992, pp. 263-267.*
Saint-Etienne et al. “Silicon Packaging and RF Solder-free Interconnect for X-band SAR T/R Module”, ACM; Alcatel Space Industries. 4 pages.*
Cinch, “CIN::APSE High Speed Interconnect Technology” downloaded from Internet Feb. 2004, 5 pages.*
“Cinch Connectors—CIN: : APSE, High-Speed Interconnect Technology”, http://www.cinch.com/products/cinapse/index.html, 4, (Nov. 4, 2000).
“Cinch Connectors—Industries, Computer and Commercial Electronics Markets Segment”, http://www.cinch.com/industries/computer/index.html, 1, (Nov. 4, 2000).
“Cinch Connectors-About Cinch”, http://www.cinch.com/about/index.html, 1, (Nov. 4, 2000).
Sathe Ajit V.
Wermer Paul H.
Intel Corporation
Myers Paul R.
Schwegman Lundberg Woessner & Kluth P.A.
LandOfFree
Solderless electronics packaging does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Solderless electronics packaging, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Solderless electronics packaging will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3427981