Soldering of a semiconductor chip to a substrate

Details Soldering of a semiconductor chip to a substrate Soldering of a semiconductor chip to a substrate

1999-10-01

2001-03-27

Ryan, Patrick (Department: 1725)

Metal fusion bonding

Process

Metal to nonmetal with separate metallic filler

C228S208000, C228S262300, C228S262600, C228S262710, C427S455000, C427S456000, C427S126500, C427S126600, C438S612000, C438S614000, C438S628000, C438S622000, C438S648000, C438S650000, C438S654000, C438S656000

Reexamination Certificate

active

06206269

ABSTRACT:

FIELD OF INVENTION
The present invention relates generally to a method and to a device produced by said method for soldering a semiconductor chip to a substrate, and particularly for soldering said semiconductor chip to a capsule in an RF-power transistor.
BACKGROUND OF THE INVENTION
At present time, chips are mounted in RF-power transistors and RF-power modules by means of a eutectic gold-silicon soldering process. The capsules used are metallised, often with nickel and a relatively thick layer of gold (2-5 &mgr;m). The chips (transistors, resistors and capacitors) to be arranged in the capsules are provided with a very thin layer of gold on their bottom surfaces. This gold layer functions to prevent oxidation of the bottom surface of the chip. When using gold-silicon, the capsule is heated to a temperature of 400-450° C. and chips are then placed individually against the capsule and rubbed or scrubbed forwards and backwards until an alloy is formed between the silicon in the chip and the gold on the capsule. It is not possible to determine precisely the point at which this alloy begins to form. This step in the process is therefore normally carried out manually, so that an operator will be able to observe when an alloy has been formed and effective soldering has been achieved.
Although all the gold present on the capsule (beneath the chip) is consumed in this soldering process, there remains a large silicon surplus in the chip. This surplus of silicon can migrate into the molten AuSi alloy and there precipitate out in the form of Si-crystals. This process is accelerated at elevated temperatures and also when mechanical rubbing, or scrubbing, is vigorous. Consequently, it is not suitable/possible to effect this scrubbing process mechanically or with ultrasound, since an excessively large amount of Si-crystals will then collect in the molten AuSi alloy. Drawbacks with an excessively large amount of Si-crystals in the molten alloy is that the melt obtains a viscous consistency and will not therefore flow outwards and effectively wet the surface.
These silicon crystals will effectively enclose any air bubbles that may have formed between chip and capsule. Such bubbles drastically impair the thermal conductivity between the chip and the capsule. The total thickness of an AuSi alloy joint formed by the gold on the capsule and the silicon in the chip can never be more than about 50% greater than the thickness of the gold. Thus, when the gold has a thickness of 4 &mgr;m, the joint will only have a thickness of about 6 &mgr;m. This places high demands on the surface flatness or smoothness of the capsule, since otherwise solder deficiencies between chip and capsule may arise.
It is generally known that additional AuSi solder can be applied between chip and capsule in the way of a preform. This is very often difficult and expensive to achieve, due to the small dimensions of such preforms. It is not possible in practice to work with preforms that have a material thickness smaller than about 25 &mgr;m. A joint of this thickness, however, will increase the thermal resistance between chip and capsule to an unacceptable degree.
SUMMARY OF THE INVENTION
One problem with known techniques for soldering semiconductor chips to a substrate, for instance a capsule in an RF-power transistor, is that the soldering process requires a manual working step in soldering each chip per se.
Another problem with known techniques is that the formation of Si-crystals impairs solder flow and results in the entrapment of bubbles. These bubbles are liable to impair the transport of heat away from the chip.
Yet another problem with known techniques is that the high solidification temperature of the SiAu solder results in high mechanical stresses between chip and capsule, therewith placing an upper limit on the size of the chip. The chip will crack if this limit is exceeded.
Still another problem with known techniques is that in order to prevent the mechanical stresses from cracking a chip, it is necessary to mount several small chips instead, therewith increasing costs in this respect.
Another problem with known techniques is that a high working temperature (400-450° C.) when mounting chips means that atoms are able to diffuse from a nickel layer beneath the gold layer up through said gold and be oxidised to cause bonding and soldering problems. This must be counteracted with a special nickel plating technique and a thick gold layer on surfaces that do not actually require a thick gold layer for AuSi soldering purposes.
Still another problem with known techniques is that the high working temperature incurred with the chip mounting process means that the parts of the actual capsule must be joined together with a hard solder or braising solder that has still a higher melting point, for instance AgCu at 790° C. Joining of metals and ceramics at this high temperature will result in the occurrence of high mechanical stresses after cooling of the joins, due to the fact that those metals and ceramics that are suitable in this context do not have mutually the same coefficient of thermal expansion. This limits the design of the capsule. For instance, it is not possible to use the optimum metals copper and the ceramic AlN in the capsule, since the coefficients of expansion of these materials are much too different from one another.
Yet another problem with known techniques is that the relatively thin solder joint formed places great demands on the surface smoothness or flatness of the capsules, since otherwise a solder deficiency will occur such that not all of the chips will be soldered effectively. This drastically impairs thermal conductivity between chip and capsule.
The present invention addresses these problems by providing a method of soldering a semiconductor chip to a substrate, such as a capsule in an RF-power transistor for instance. The semiconductor chip is first provided with an adhesion layer consisting of a first material composition. A solderable layer of a second material composition is then disposed on this adhesion layer. There is then disposed on the solderable layer an antioxidation layer consisting of a third material composition. A layer of solder consisting of a gold-tin alloy is then coated on the antioxidation layer. The chip is placed on a solderable capsule surface, via said gold-tin solder. The capsule and the chip are exposed to an inert environment to which there is added a reduction gas and the capsule and chip are subjected to pressure that is substantially beneath atmospheric pressure, while heating the gold-tin alloy in the solder to a temperature above its melting temperature. The gas pressure is increased whilst the gold-tin solder is in a molten state and the temperature is lowered upon exceeding a predetermined gas pressure, so that the gold-tin alloy will solidify.
In accordance with one preferred embodiment of the inventive method, the first material composition is titanium-tungsten composition (TiW), the second material composition is nickel (Ni), and the third material composition is gold (Au).
In another preferred embodiment of the inventive method, the first material composition is titanium (Ti), the second material composition is platinum (Pt) and the third material composition is gold (Au).
According to another preferred embodiment of the inventive method, composition of the gold-tin solder is compensated by the gold from the capsule, so that a final alloy composition will lie as close as possible to the eutectic melting point.
In another preferred embodiment of the inventive method, the gold-tin alloy in the solder has a composition of 75% Au and 25% Sn when the capsule includes a 3-4 &mgr;m thick layer of gold to which the chip shall be soldered.
According to still another preferred embodiment of the inventive method, the reducing gas is formic acid in a vapor state.
In one embodiment of an RF-power transistor according to the invention, the transistor includes at least one RF-power semiconductor chip and a capsule. The semiconductor chip is provided with an adhesion layer

Affiliated with

Also associated with

Rating

Soldering of a semiconductor chip to a substrate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Soldering of a semiconductor chip to a substrate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Soldering of a semiconductor chip to a substrate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2488796