Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
2002-10-23
2004-08-10
Thai, Luan (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S750000, C257S751000, C257S761000, C257S762000, C257S763000, C257S764000, C257S765000, C257S766000, C257S737000, C257S778000, C257S779000
Reexamination Certificate
active
06774495
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a solder terminal structure and a method for fabricating the same and, more particularly, to a solder terminal structure and a fabrication method thereof to improve the reliability of a solder terminal.
2. Description of the Related Art
A so-called flip chip bonding technology is commonly used for semiconductor device packaging. The flip-chip bonding technology enables electrical and physical connection between a semiconductor chip and a substrate such as a ceramic substrate or a circuit board by simultaneously connecting corresponding terminals of the semiconductor chip and the substrate using solder balls or solder columns.
FIG. 1
is a cross-sectional view of a solder bump assembly to illustrate the connections between a semiconductor chip and a substrate using a conventional flip-chip bonding technology.
Referring to
FIG. 1
, solder balls
45
or solder bumps
40
electrically connect electrode (bond) pads
20
on a semiconductor device
30
and electrode pads
11
on a substrate
10
. The solder balls
45
or solder bumps
40
are formed on one side or both sides of the semiconductor device
30
or substrate
10
and are connected to the corresponding electrode pads
20
,
11
exposed through insulating films
50
that cover the semiconductor device
30
and the substrate
10
.
A reference numeral “51” indicates an epoxy resin filled between the semiconductor device
30
and the substrate
10
to protect the semiconductor device
30
and substrate
10
from harmful environmental conditions such as electrical and physical impact.
To precisely control the volume and composition of the solder, the solder terminals are manufactured by selectively depositing or plating the solder using a mask formed of a metal or photoresist.
The solder bumps
40
formed on the semiconductor device
30
are generally separated into two areas of a solder terminal metal layer and a connection layer.
On the other hand, because metals such as aluminum, chrome, molybdenum or tungsten employed for wiring of the semiconductor device
30
do not flow or react well, the adhesion between the solder and the adjacent layers has been somewhat problematic.
FIG. 2A
is a plan view showing the electrode pads
20
formed on the surface of the semiconductor device
30
and the solder bumps
40
connected to the electrode pads
20
. Referring to
FIG. 2A
, the plurality of electrode pads
20
formed on the surface of the semiconductor device
30
are isolated from each other and exposed through the insulating layer
50
. And a solder bump
40
is attached to the electrode pads
20
through the solder terminal (not shown). The position, number and size of the solder terminals are determined by a design rule of the semiconductor device
30
and the substrate
10
, module reliability and the solder terminal forming process.
Conventionally, the total number of mutual connections used in a Very Large Scale Integration (VLSI) is about 1,000 and is expected to increase further. In line with current demands for high-speed and high-performance semiconductor devices, it is required that the electrode pads
20
of the semiconductor
30
have very high thermal and mechanical reliability.
FIG. 2B
is an exemplary view showing the electrode pad
20
and a solder bump terminal on the semiconductor device
30
according to the prior art With reference to
FIG. 2B
, the semiconductor device
30
has at least one patterned wiring and a predetermined area of the wiring is exposed through the insulating layer
50
on the surface of the semiconductor device
30
to form the electrode pad
20
. An adhesion metal layer
60
is formed on the insulating layer
50
and the electrode pad
20
.
Also, a solder bonding layer
80
formed of a material for soldering forms a metallurgical bond by reacting with solder when the solder is heated. An intermediate layer
70
is formed between the adhesion metal layer
60
and solder bonding layer
80
to increase the bonding strength between the adhesion metal layer
60
and solder bonding layer
80
, if necessary.
On the other hand, the solder bonding layer
80
reacts with at least one component of the solder bump
40
when the solder is melted, and forms an inter-metallic compound. When the solder is repeatedly melted numerous times, a Cu—Sn inter-metallic compound (not shown) grows thick and the metallurgical microstructure becomes coarse and discontinuous.
Therefore, in the prior art, if such a reaction continues, all of the solder bonding layer
80
can be changed into an intermetallic compound and a bonding strength of the solder bump
40
and adhesion metal layer
60
undesirably declines.
To prevent such a reduction in bonding strength of the solder bump
40
and the adhesion metal layer
60
, the intermediate layer
70
is inserted between the solder bump
40
and adhesion metal layer
70
as discussed above. Conventionally, Cr—Cu is employed to form the intermediate layer
70
.
With the conventional intermediate layer formed of, e.g., Cr—Cu, however, the Cu component in the Cr—Cu reacts with Sn in the solder and is thus removed, thus reducing the adhesion strength of the solder, especially, the strength of the solder where the solder contacts the other adjacent layers.
Further, with the prior art structure, there can be harmful reaction or interdiffusion between the electrode pad and the solder bonding layer, or between the adhesion layer and the solder bonding layer, which significantly degrades the device characteristics.
In addition, during the reliability test of the semiconductor devices, a probe mark may be left on the electrode (bond) pad. Because the area of the electrode pad where the probe mark is left is relatively thin, if a solder terminal of another material is directly mounted thereon, the electrode pad may be damaged by stress and chemical reaction between different materials.
SUMMARY OF THE INVENTION
Therefore, the present invention provides a solder terminal and a fabrication method thereof for solving problems and disadvantages of the conventional solder terminal structure.
According to an embodiment of the present invention, a solder terminal and a fabrication method thereof are provided to solve the problem discussed above.
The present invention also provides a solder terminal and a fabrication method thereof for acting as a solder dam that prevents a solder from being wetted and spreading without forming an additional metal layer for a solder terminal.
Therefore, the aluminum film of the electrode pad that becomes thinner by the probe mark can be compensated to the original thickness by mounting an adhesion metal layer of aluminum, which is identical to the material of the electrode pad, on the electrode pad. Thus, the problem can be solved and the stress can be minimized.
Additionally, the present invention provides a solder terminal structure and a fabrication method thereof, which can prevent the diffusion of aluminum from the electrode pad due to thermal loading, using a thermal diffusion barrier. Also, the thermal diffusion layer prevents the diffusion of aluminum from the electrode pad by electrical loading in semiconductor reliability test such as high temperature operation life (HTOL) acceleration test.
According to an embodiment of the present invention, a solder terminal structure comprises a plurality of electrode pads separated by an insulating layer on the surface of the semiconductor device chip, an adhesion metal layer formed over the electrode pads and the insulating layer adjacent to the electrode pad, a thermal diffusion barrier formed on the adhesion metal layer, a solder bonding layer formed on the thermal diffusion barrier and a solder bump formed on the solder bonding layer.
According to yet another embodiment of the present invention, a fabricating method comprises forming an insulating layer on a surface of a semiconductor device chip and exposing a plurality of electrode pads which are separated from each other by selectively etching the insulating layer,
CCUBE Digital Co., Ltd.
Marger & Johnson & McCollom, P.C.
Thai Luan
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