Solder limiting layer for integrated circuit die copper bumps

Details Solder limiting layer for integrated circuit die copper bumps Solder limiting layer for integrated circuit die copper bumps

2011-07-19

2011-07-19

Wilczewski, Mary (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S778000, C257S779000, C257S781000, C257SE23021, C257SE23023, C438S613000

Reexamination Certificate

active

07982311

ABSTRACT:
An apparatus comprises a semiconductor substrate having a device layer, a plurality of metallization layers, a passivation layer, and a metal bump formed on the passivation layer that is electrically coupled to at least one of the metallization layers. The apparatus further includes a solder limiting layer formed on the passivation layer that masks an outer edge of the top surface of the metal bump, thereby making the outer edge of the top surface non-wettable to a solder material.

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