Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-03-21
2001-12-18
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S358000, C257S360000, C257S363000
Reexamination Certificate
active
06331726
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an electrostatic discharge (ESD) protection circuits; and, more particularly, to ballasting resistors for providing ESD protection for silicon on-insulator (SOI) devices.
DESCRIPTION OF THE PRIOR ART
MOSFET scaling on bulk silicon has been the primary focus of the semiconductor and microelectronics industry for achieving CMOS chip performance and density objectives. The shrinking of MOSFET dimensions for high density, low power and enhanced performance requires reduced power-supply voltages. Because power consumption (P) is a function of capacitance (C), power supply voltage (V) and transition frequency (f) where P=fCV
2
, the focus has been on reducing both C and V as the transition frequency increases. The components of the MOSFET capacitance (C) consist of diffusion and gate capacitances. As a result, dielectric thickness and channel length are scaled with power-supply voltage. Power-supply reduction continues to be the trend for future low-voltage CMOS. However, with power-supply reduction, transistor performance is severely impacted by both junction capacitance and the MOSFET body effect at lower voltages. As technologies scale below 0.25 Tm channel lengths, to 0.15 and 0.1 Tm, short-channel effects control, gate resistance, channel profiling and other barriers become an issue for advanced CMOS technologies. While significant success has been achieved with successive scaling of bulk CMOS technology, the manufacturing control issues and power consumption will become more difficult to deal with.
Using silicon-on-insulator (SOI) substrates, many of the concerns and obstacles of bulk-silicon CMOS can be eliminated at low power-supply voltages. CMOS-on-SOI has significant advantages over bulk CMOS technology and will achieve the scaling objectives of low power and high performance for future technologies. CMOS-on-SOI provides low power consumption, low leakage current, low capacitance diode structures, good sub-threshold I-V characteristics (better than 60 mV/decade), a low soft error rate from both alpha particles and cosmic rays, good access times, and other technology benefits. SOI has not become a mainstream CMOS technology because of the rapid improvement in bulk CMOS technology performance, however, it is a future contender for mainstream CMOS applications. One of the barriers to implementing SOI is the “floating body” issue. Another barrier is electrostatic discharge protection (ESD).
Presently, there are multiple strategies for ESD protection of SOI structures. One of these is to use bulk ESD protection circuits on an SOI wafer. According to a semiconductor process proposed by Kawai, disclosed in U.S. Pat. No. 4,889,829, entitled “METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE HAVING A SILICON-ON-INSULATOR STRUCTURE”, bulk transistors are in the substrate and SOI transistors are on the insulating film. If this is possible, bulk ESD devices can be designed without any new SOI-specific ESD issues. This proposal has significant topography, which would make it unacceptable for high density and planarity integration issues. In addition, it forces special semiconductor processing for the sole purpose of providing ESD protection. Sun (U.S. Pat. No. 5,399,507 entitled “FABRICATION OF MIXED THIN FILM AND BULK SEMICONDUCTOR SUBSTRATE FOR INTEGRATED CIRCUIT APPLICATIONS”) proposed a mixed thin film where ESD devices are constructed in bulk and where the oxygen implant is masked and SOI devices are built over the insulating layer. This concept eliminates planarity concerns but leads to silicon dislocation, which is unacceptable from a manufacturing perspective. A disadvantage of these bulk strategies is that charged-device model (CDM) failures can occur more frequently because ESD networks now are in bulk, whereas in an SOI technology, bulk substrate charging from CDM mechanisms is less of a concern. With SOI, significant freedom exists to develop bipolar technology side-by-side with CMOS technology. However, a significant cost results in each of these implementations, which is neither acceptable nor practical to address.
Another technique to limit the current through the transistors is to put an impedance in series with the MOSFET transistors, either by directly integrating it with the sources or drains of the MOSFETs, thereby adding drain or source resistances or building what is called standard resistors in series with these elements.
When these structures undergo thermal runaway, they typically find a defective or a hot spot which then leads to current constriction through a physically smaller region of the device, which is much physically smaller than the full width of transistor. So the technique to distribute the current through the full transistor and avoid thermal runaway is known as resistor ballasting.
Resistor ballasting is a technique which reduces a plurality of resistors with every leg of a transistor or subdivision of the transistor into multiple resistors in order to prevent the electric current constriction through a given defect in the MOSFET transistor during high current phenomenon.
With the voltage at very low currents, any silicon bulk resistor would basically begin to follow Ohm's law, which is a linear characteristic, assuming that the velocity of carriers increases linear with the electric field. As the voltage increases, however, the relationship between the velocity and the electric field becomes non-linear to the saturation. So when electric field is high enough that the carriers undergo velocity saturation, these resistor elements have a tendency to saturate as shown in FIG.
1
. As the voltage further increases, avalanche multiplication occurs across the resistor structure and actually get a snap-back phenomena in the resistor itself and it will undergo an avalanche process.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide an improved SOI (silicon-on-insulator) ESD (electrostatic discharge) protection device capable of increasing an impedance thereof as the voltage applied to a device or a circuit to be protected increases, thereby limiting the current through the circuit.
In accordance with one aspect of the present invention, there is provided a circuit comprising a device for limiting a current, further comprising:
a current path having a cross section for passing the current therethrough; and
a pinching means responsive to an applied voltage for reducing the cross section as an amplitude of the applied voltage increases, thereby causing an impedance of the device to increase.
In accordance with another aspect of the present invention, there is provided a circuit comprising a device formed on an insulating layer for limiting a current, further comprising:
an input node and an output node formed of a semiconductor material of a first doping type;
plurality of discrete semiconductor regions of a second doping type; and
a semiconductor region of the first doping type, the nodes and the semiconductor regions of the second doping type are coupled each other by the semiconductor region of the first doping type formed therebetween,
wherein the semiconductor regions of the first and the second types are reverse-biased such that depletion regions inside the semiconductor region of the first doping type increase with an increasing amplitude of an applied voltage to thereby reduce a cross-sectional area through which the current passes.
Further, the present invention provides a structure comprising:
a substrate wafer;
a buried oxide layer on said substrate wafer;
a silicon film on said buried oxide layer;
a H-shape MOSFET gate structure with a gate dielectric;
a spacer;
a polysilicon film;
first and second doped regions of a first conductivity defined by said H-shape MOSFET gate structure;
a channel region of a second conductivity under said gate dielectric;
a first body contact of a second conductivity;
a second body contact of a second conductivity; and
a resistive element formed between said first body contact and said second body contact.
REFERENCE
International Business Machines - Corporation
Ngo Ngan V.
Rosenman & Colin, LLP.
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