SOI/semiconductor heterostructure fabrication by wafer bonding

Details SOI/semiconductor heterostructure fabrication by wafer bonding SOI/semiconductor heterostructure fabrication by wafer bonding

1993-05-19

1994-12-13

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

257616, 257618, 257754, 257768, H01L 2906, H01L 2904, H01L 2712, H01L 2702

Patent

active

053731840

ABSTRACT:
This is a method of forming a semiconductor-on-insulator wafer from two individual wafers. The method comprises: forming a layer of metal (e.g. titanium 24) on a first wafer; forming an insulator (e.g. oxide 32) on a second wafer; forming a bonding layer (e.g. poly 38) over the insulator; anisotropically etching the bonding layer forming chambers in the bonding layer; stacking the first and second wafers with the metal against the second wafer's bonding layer; forming a chemical bond between the metal layer and the bonding layer (e.g. between the titanium 20 and the poly 38) in a vacuum chamber, thereby creating micro-vacuum chambers (42) between the wafers; selectively etching the second wafer to form a thin semiconductor layer ( e.g. epi layer 30). This is also a semiconductor-on-insulator wafer. The wafer comprises: a substrate (e.g. semiconductor substrate 20); a layer of metal (e.g. titanium 24) and semiconductor ( e.g. silicide 40) over the substrate; a bonding layer (e.g. poly 38) over the metal and semiconductor, with micro-vacuum chambers (42) in the bonding layer; an insulator (e.g. oxide 32) over the bonding layer; and a single-crystal semiconductor layer (e.g. epi layer 30) over the insulator.

REFERENCES:
IEDM Digest, Dec. 1985, pp. 684-687, by Lashy et al.
IEEE Electron Devices Society Program of Annual Conference, Jun. 1988, by Arimoto et al. vol. 28, #8, pp. 1426-1443, by Haisma et al. Aug. 1989.
Fujitsu Sci. Tech. Journal, vol. 24, #4, pp. 408-417 by Gotou et al., Dec. 1988.

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