Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – On insulating substrate or layer
Reexamination Certificate
2001-01-30
2002-09-03
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
On insulating substrate or layer
Reexamination Certificate
active
06444534
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to making silicon-on-insulator (SOI) semiconductor wafers, and in particular to a gettering method for use with an SOI semiconductor device.
BACKGROUND OF THE INVENTION
Recently, semiconductor-on-insulator (SOI) wafers increasingly have been used in very-large scale integration (VLSI) or ultra-large scale integration (ULSI) of semiconductor devices. An SOI wafer typically has a layer of silicon on top of a layer of an insulator material. In an SOI integrated circuit, essentially complete device isolation may be achieved using conventional device processing methods by surrounding each device, including the bottom of the device, with an insulator. One advantage which SOI wafers have over bulk silicon wafers is that the area required for isolation between devices on an SOI wafer is less than the area typically required for isolation on a bulk silicon wafer.
SOI offers other advantages over bulk silicon technologies as well. For example, SOI offers a simpler fabrication sequence compared to a bulk silicon wafer. Devices fabricated on an SOI wafer may also have better radiation resistance, less photo-induced current, and less cross-talk than devices fabricated on bulk silicon wafers. Devices within integrated circuits are very sensitive to the presence of even minute concentrations of some impurities. For example, metals, such as copper, nickel, silver, gold, or iron, within the active region of a device typically degrade several device characteristics, including leakage current and oxide breakdown voltage. These and other metals rapidly diffuse through bulk silicon at temperatures typical of semiconductor device fabrication processes. Such impurities in the active region of the SOI wafer migrate out of the active region more slowly than they migrate in bulk silicon because the insulation region tends to retard impurities in the active layer from diffusing into the bulk silicon beneath the insulation region. Some impurities which have migrated to, but have been retarded by the insulation region, may re-migrate into the whole of the active region during subsequent processing steps. Accordingly, SOI wafers are prone to device and reliability problems caused by the presence of impurities that remain in the active region.
Methods of gettering a silicon substrate are well known. Gettering is used to remove contaminants (usually heavy metals) from regions of the circuit where their presence would degrade device performance. Most all the transition metals, such as gold, copper, iron, titanium, nickel, etc., have been reported as possible contaminants. It is desirable to reduce the presence of such contaminants in the active regions in order to reduce, for example, reverse junction leakage, improve bipolar transistor gain, and increase refresh time in dynamic metal oxide semiconductor (MOS) memories. There are two common forms of gettering: intrinsic gettering and extrinsic gettering.
Intrinsic gettering involves forming gettering sites in the bulk of a semiconductor substrate, generally below the active regions near the frontside surface of the semiconductor substrate. In silicon substrates (wafers) manufactured using the Czochralski (Cz) method, intrinsic gettering generally includes an initial denuding step (for wafers without silicon epitaxial layers) followed by a nucleation step, and then a precipitation step. Denudation, nucleation, and precipitation, in combination, form lattice dislocations in the silicon bulk below the active regions. The dislocations serve to trap heavy metal ions at the dislocation sites, away from the overlying active regions.
Extrinsic gettering, on the other hand, generally involves gettering near the backside surface of a silicon substrate. There are several methods used to perform extrinsic gettering. Two common methods include (i) diffusing phosphorous into the backside surface of a silicon wafer, and/or (ii) depositing polycrystalline silicon (polysilicon) on the backside surface of a silicon wafer. Diffusion processes utilizing extrinsic gettering techniques such as backside phosphorous diffusion and polysilicon deposition is described in Runyan, et al., Semiconductor Integrated Circuit Processing Technology, (Addison-Wesley Publishing Co., 1990), pp. 428-442; and, DeBusk, et al., “Practical Gettering in High Temperature Processing”, Semiconductor International, (May 1992) (both of which are herein incorporated by reference for their teachings relating to gettering).
Extrinsic gettering has been applied to the frontside surface of polycrystalline silicon wafers, in which phosphorus doping of contact layers is used to obtain frontside (or topside) gettering of diffused impurities or contaminants.
In SOI wafer technology, however, the use of polysilicon in direct contact with the back of the SOI wafer is not an effective gettering scheme, since the buried oxide layer will act as a diffusion barrier, causing contaminants to become trapped in the SOI film. The use of topside gettering by phosphorus doping of contact layers applied late in the fabrication process has not been effective in SOI technology due to the fact that it cannot prevent contamination during earlier stages of the process. Furthermore, since such topside gettering is applied late in the fabrication process, it can only protect portions of the circuit from which impurities can be gettered from above the device. Such gettering leaves the device susceptible to contaminants which later migrate from other portions covered by device elements from which the impurities cannot directly be gettered from the topside.
Once a device has been formed on an SOI semiconductor wafer, the problem of impurities in the active regions of the device remains, and the difficulty of gettering the impurities at this point in the fabrication process of the SOI semiconductor device is exacerbated by the presence of the device itself. In particular, in devices such as SOI MOSFETs, the source region, drain region, gate region and the portion of the body region which forms the channel region are vulnerable to the untoward effects of impurities in the semiconductor materials forming these regions. Furthermore, even when impurities have been gettered from the active region of an SOI wafer prior to fabrication of the semiconductor device thereon, the fabrication process may introduce impurities into the active region and/or portions of the semiconductor device itself. Thus, a method which getters impurities prior to formation of a semiconductor device, such as that disclosed in U.S. Pat. No. 5,753,560, fails to provide complete gettering in the semiconductor at or near completion of its fabrication.
The aforementioned problems resulting from both the nature of the SOI wafer and from the deficiencies in prior art gettering methods remain. The combination of these factors has presented a significant problem in gettering impurities from the active regions of SOI semiconductor devices at or near completion of the fabrication process. Thus, there has been a need for a method of gettering impurities from SOI semiconductor device at or near completion of the fabrication process.
SUMMARY OF THE INVENTION
A method of gettering of the active regions of semiconductor devices formed on SOI wafers is the subject of this application.
In a first embodiment, the present invention relates to a method of manufacturing a semiconductor device on an SOI wafer, comprising the steps of:
providing a silicon-on-insulator semiconductor wafer having a silicon film formed on an insulator layer;
forming at least one semiconductor device in the silicon film, the at least one semiconductor device including at least one semiconductor element, an interlayer dielectric over the semiconductor device, and at least one opening passing through the interlayer dielectric;
implanting inert atoms into one or more of the at least one semiconductor element by passing the inert atoms through the opening at an energy and at a dose sufficient to form a damaged region in one or more of the at least one semiconduct
LandOfFree
SOI semiconductor device opening implantation gettering method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with SOI semiconductor device opening implantation gettering method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SOI semiconductor device opening implantation gettering method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2909721