Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – Including additional component in same – non-isolated structure
Reexamination Certificate
2001-01-08
2002-08-06
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
Including additional component in same, non-isolated structure
C257S360000, C257S361000
Reexamination Certificate
active
06429505
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device suitable for use as a protection circuit for protecting an integrated circuit against electrostatic discharge (ESD), and in particular to improvements for the purposes of enhancing current drivability and accelerating a turn-on operation.
2. Description of the Background Art
Conventionally, ESD protection circuits have been utilized for preventing integrated circuits formed in semiconductor substrates from being damaged by the application of a positive or negative high voltage, as overshooting or undershooting input voltage, due to the accumulation of electrostatic charge in the human body or machinery. Semiconductor controlled rectifiers (generally referred to as “SCRs”) are a kind of such ESD protection circuits.
FIGS. 42 and 43
are a cross-sectional view and a circuit diagram of a conventional SCR, respectively. This SCR
200
is formed in an SOI substrate including a supporting substrate
201
, a buried insulation film
202
, and an SOI (semiconductor on insulator) layer
203
and is utilized as a protection circuit for protecting an internal circuit
212
, which is an integrated circuit being protected, against ESD. In the main surface of the SOI layer
203
, STI (shallow trench isolation) as a partial isolating layer
204
which does not reach the buried insulation film
202
is selectively formed, by which a plurality of element regions SR
100
, SR
101
, and SR
102
are partially isolated from each other.
The SOI layer
203
includes a p layer
205
which is adjacent to the buried insulation film
202
. In the element region SR
100
of the SOI layer
203
, an n layer
206
is selectively formed in the main surface, and an n
+
layer
207
, a p
+
layer
208
, and an n
+
layer
209
are also selectively formed in the main surface to cover the surface of the p layer
205
. In the element region SR
101
, an n
+
layer
210
is formed in the main surface. In the element region SR
102
, a p
+
layer
211
is formed in the main surface.
The p
+
layer
208
, the n layer
206
, and the p layer
205
form the collector, base, and emitter of a pnp bipolar transistor NB
100
, respectively, while the n layer
206
, the p layer
205
, and the n
+
layer
210
form the collector, base, and emitter of an npn bipolar transistor PB
100
, respectively. Further, the p
+
layer
208
forms a resistive element R
100
while the n
+
layer
210
forms a resistive element R
101
.
In this fashion, the SCR
200
comprises the two bipolar transistors NB
100
and PB
100
of different conductivity types, the collector of one transistor being connected to the base of the other transistor and the base of one transistor being connected to the collector of the other transistor. The bipolar transistors NB
100
and PB
100
thus constitute a positive feedback circuit.
The n
+
layer
207
and the p
+
layer
208
are connected through a node (a connection in the wiring) N
100
to an anode A, and the n
+
layer
210
and the p
+
layer
211
are connected through a node N
101
to a cathode C. The anode A is connected to a wire
213
for use in transmission of an input signal T
1
to the internal circuit
212
.
FIG. 44
is a graph schematically showing the current-voltage characteristics of the SCR
200
. When the anode-cathode voltage (the potential of the anode A relative to the cathode C) V
AC
rises from 0 in a positive direction, the SCR
200
is kept in a high impedance state where the current I
1
hardly flows, until the voltage V
AC
reaches a switching voltage V
S
. However, when the voltage V
AC
exceeds the switching voltage V
S
, the SCR
200
quickly transits to a low impedance state where a large current flows. The SCR
200
will be kept in this low impedance state until the current I
1
flowing through the SCR
200
falls beneath a holding current I
H
.
Thus, when ESD causes the voltage of the input signal T
1
(
FIG. 42
) to overshoot the source voltage V
DD
to V
DD
+&Dgr;V
DD
, the anode-cathode voltage V
AC
of the SCR
200
exceeds the switching voltage V
S
before the internal circuit
212
is broken and thus the SCR
200
transits from the high impedance state to the low impedance state. Then, current larger than the holding current I
H
flows through the SCR
200
and the voltage of the input signal T
1
decreases before the overshoot voltage V
DD
+&Dgr;V
DD
is transmitted to the internal circuit
212
.
A surge voltage caused by ESD is high but its amount of charge is limited; therefore, the current flowing through the SCR
200
will fall beneath the holding voltage I
H
in due course. As a result, the SCR
200
returns back to its initial or high impedance state from the low impedance state. In this way, the SCR
200
protects the internal circuit
212
against damage from ESD.
U.S. Pat. No. 6,015,992 discloses an SCR which comprises MOSFETs (MOS field-effects transistors) formed in an SOI substrate.
FIG. 45
is a perspective view of the SCR disclosed in this U.S. Patent when viewed angularly from the above, and
FIG. 46
is a cross-sectional view of this SCR
300
of
FIG. 45
, taken along the section line Z
1
-Z
2
.
FIG. 47
is a circuit diagram of the SCR
300
of FIG.
45
.
The SCR
300
is also formed in an SOI substrate including a supporting substrate
301
, a buried insulation film
302
, and an SOI layer
350
. In the main surface of the SOI layer
350
, STI as a full isolating layer
303
which reaches the buried insulation film
302
is selectively formed, by which a plurality of element regions SR
200
, SR
201
, SR
202
, and SR
203
are fully isolated from each other.
In the element region SR
200
, p
+
layers
308
,
309
and a p layer
304
are formed. The p layer
304
forms a resistive element R
200
. In the element region SR
203
, n
+
layers
316
,
317
and an n layer
307
are formed. The n layer
307
forms a resistive element
210
.
In the element region SR
201
, a p layer
305
, n layers
318
,
319
, n
+
layers
310
,
311
, and a p
+
layer
312
are formed. The n layer
318
and the n
+
layer
310
form the source of an n-channel MOSFET, and the n layer
319
and the n
+
layer
311
form the drain thereof. In particular, the n layers
318
and
319
make extensions which are parts of the source/drain (herein a pair of source and drain is generically referred to as a “source/drain”).
Part of the p layer
305
is opposed to a gate
323
with a gate insulating film
322
therebetween. Further, sidewalls or insulators
324
,
325
are formed on the side surfaces of the gate
323
. The p layer
305
and the p
+
layer
312
form the body of the n-channel MOSFET. Especially, a portion of the p layer
305
of the body which is sandwiched between the source/drain
310
,
318
,
311
and
319
and is opposed to the gate
323
functions as a channel. Also, the p
+
layer
312
of the body where connections with wiring are made is called a body contact region.
The n
+
layer
310
, the p layer
305
(and the p
+
layer
312
), and the n
+
layer
311
form the emitter, base, and collector of an npn bipolar transistor PB
200
, respectively. That is, the element region SR
201
has formed therein the bipolar transistor PB
200
as a parasitic bipolar transistor of the n-channel MOSFET.
The element region SR
202
is formed to be symmetrical to the element region SR
201
with respect to the conductivity type. More specifically, an n layer
306
, p layers
320
,
321
, p
+
layers
313
,
314
, and an n
+
layer
315
are formed in the element region SR
202
. The p layer
320
and the p
+
layer
313
form the drain of a p-channel MOSFET, and the p layer
321
and the p
+
layer
314
form the source thereof. In particular, the p layers
320
and
321
make extensions which are parts of the source/drain.
Part of the n layer
306
is opposed to a gate
327
with a gate insulating film
326
therebetween. Further
Ho Tu-Tu
Mitsubishi Denki & Kabushiki Kaisha
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