Active solid-state devices (e.g. – transistors – solid-state diode – Mosfet substrate bias
Reexamination Certificate
1999-12-06
2001-08-28
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Mosfet substrate bias
C257S347000, C438S149000
Reexamination Certificate
active
06281593
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a thin film siliconon-insulator semiconductor device, and more particularly to a SOI MOSFET having contact to the FET body. In particular, according to the present invention, a body connection region is provided that extends deeper into the substrate under the device's shallow trench isolation region and then back upwards towards a surface of the substrate through a contact region. This body connection region provides an electrical connection to the body of the SOI device. In addition, the present invention relates to a process for fabricating the SOI MOSFET devices of the present invention.
BACKGROUND OF INVENTION
Field effect transistors (FETs) have become the dominant active device for very large scale integration (VLSI) and ultralarge scale integration (ULSI) applications in view of the high performance, high density and low power characteristics of integrated circuit FETs. In fact, much research and development has involved improving the speed and density of FETs and on lowering their power consumption.
The most common configuration of FET devices is the MOSFET which typically comprises source and drain regions in a semiconductor substrate at a first surface thereof, and a gate region located therebetween. The gate includes an insulator on the first substrate surface between the source and drain regions, with a gate electrode or contact on the insulator. A channel is present in the semiconductor substrate beneath the gate electrode, and the channel current is controlled by a voltage at the gate electrode.
More recently, in an attempt to improve the performance of FET devices, such as reducing parasitic capacitance, silicon-on-insulator (SOI) technology has become an increasingly important technique. SOI technology deals with the formation of transistors in a relatively thin monocrystalline semiconductor layer which overlays an insulating layer. The insulating layer is typically formed on an underlying substrate which may be silicon. In other words, the active devices are formed in a thin semiconductor on insulator layer rather than in the bulk semiconductor of the device. Currently, silicon is most often used for this monocrystalline semiconductor layer in which devices are formed. However, it will be understood by those skilled in the art that other monocrystalline layers such as germanium or gallium arsenide may be used. Accordingly, any subsequent reference to silicon will be understood to include any semiconductor material.
High performance and high density integrated circuits are achievable by using the SOI technology because of the reduction of parasitic elements present in integrated circuits formed in bulk semiconductors. For example, for a MOS transistor formed in bulk, parasitic capacitance is present at the junction between the source/drain regions and the underlying substrate, and the possibility of breakdown of the junction between source/drain regions and the substrate regions also exist. A further example of parasitic elements is present for CMOS technology in bulk, where parasitic bipolar transistors formed by n-channel and p-channel transistors in adjacent wells can give rise to latch-up problems. Since SOI structures significantly alleviate parasitic elements, and increase the junction breakdown tolerance of the structure, the SOI technology is well suited for high performance and high density integrated circuits.
The first application of SOI technology was silicon-on sapphire. Most recent efforts have been directed towards growing monocrystalline silicon on top of a silicon dioxide layer formed on a silicon wafer. See for example the publications entitled “Ultra-high Speed CMOS Circuits in Thin Simox Films” by Camgar et al, Vol. 89, IEDM, pp. 829-832, 1989 and “Fabrication of CMOS on Ultrathin SOI Obtained by Epitaxial Lateral Overgrowth and Chemical-Mechanical Polishing”, Shahidi et al, Vol. 90, IEDM, pp. 587-590, 1990.
Furthermore, SOI technology allows for the mapping of standard advanced technologies into a SOI technology without significant modifications. SOI process techniques include epitaxial lateral overgrowth (ELO), lateral solid-phase epitaxy (LSPE) and full isolation by porous oxidized silicon (FIPOS). SOI networks can be constructed using the semiconductor process of techniques of separation by implanted oxygen (SIMOX) and wafer-bonding and etch-back (SIBOND) because they achieve low defect density, thin film control, good minority carrier lifetimes and good channel mobility characteristics. Structural features are defined by shallow-trench isolation (STI). Shallow-trench isolation eliminates planarity concerns and multidimensional oxidation effects, such as LOCOS birds beak, thereby allowing technology migration and scaling to sub 0.25&mgr; technologies.
Although the floating body of a SOI MOSFET provides a number of advantages, including the absence of the reverse-body effect, there are some other problems that such structures possess. Included among the more important problems caused by the device floating body are reduction of the standard saturated threshold voltage and large fluctuations in the linear threshold voltage of the device. The floating-body effects cause problems in circuits that require good threshold voltage (Vt) control and threshold voltage (Vt) matching.
SUMMARY OF INVENTION
The present invention provides for significantly reducing these floating-body problems of SOI devices. In particular, according to the present invention, a body connection region is provided that electrically connects the body of the MOSFET to a contact region. More particularly, the present invention relates to an integrated circuit chip comprising:
a substrate layer on an insulator layer including portions wherein the insulator layer is at an increased depth below the silicon surface which forms a plurality of deeper SOI regions beneath a corresponding plurality of dielectric shallow trench regions in the substrate layer;
a plurality of FETs formed in the substrate layer and spaced apart by dielectric isolation regions in the substrate extending down to the insulator layer;
the FETs each including a gate and a body formed in the substrate layer under the gate of the FET in electrical communication with one of the deeper SOI regions;
a body contact of said each of the FETs formed on a second side of said one of the dielectric shallow trench regions in electrical communication with said one of the deeper SOI regions.
The present invention also relates to a method for fabricating the devices of the present invention. In particular, the method according to the present invention comprises providing a semiconductor substrate, providing a mask on the semiconductor substrate and delineating the mask by providing open regions therein corresponding to subsequently to be formed deep buried oxide regions, implanting oxygen ions through the mask and through the open regions in the mask and thermally annealing to form buried oxide regions, whereby the regions protected by the mask form shallow buried oxide regions and the open regions form deep buried oxide regions.
The mask is removed and dopants of a first type are implanted into the substrate at the locations of the deep buried oxide layer and the channel regions for the subsequently to be created gate structures. Shallow trench isolation is provided for isolating FET structures from each other. A gate conductor is located above the gate insulating layer, and source and drain regions of a second conductivity type opposite from the conductivity type of the semiconductor SOI layer is provided.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in v
Brown Jeffrey Scott
Bryant Andres
Gauthier Jr. Robert J.
Voldman Steven Howard
Connolly Bove Lodge & Hutz
Flynn Nathan
International Business Machines - Corporation
Quinto Kevin
Shkurko Eugene I.
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