SOI hybrid structure with selective epitaxial growth of silicon

Details SOI hybrid structure with selective epitaxial growth of silicon SOI hybrid structure with selective epitaxial growth of silicon

2002-12-31

2003-10-21

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

On insulating substrate or layer

C438S309000, C438S318000, C438S341000, C438S353000, C438S360000, C438S151000

Reexamination Certificate

active

06635543

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure.
2. Related Art
A Dynamic Random Access Memory (DRAM) cell coupled to a silicon-on-insulator (SOI) structure is characterized by a significant degradation of DRAM capacitor charge retention time as compared with a DRAM cell on a bulk silicon substrate. A method and structure is needed for coupling a DRAM cell to a SOI substrate without having the significant degradation of the DRAM capacitor charge retention time.
Bipolar junction and Complementary Metal Oxide Silicon (BiCMOS) devices have bipolar transistors typically located more than 200 nm into the depth of the structure of the BiCMOS device which is deeper than the buried oxide layer of a typical SOI substrate. As a result, an integration of SOI Complementary Metal Oxide Semiconductor (CMOS) devices and bipolar transistors of BiCMOS devices is problematic. A method and structure is needed for integrating SOI CMOS devices and bipolar transistors of BiCMOS devices.
SUMMARY OF THE INVENTION
The present invention provides a method for forming an electronic structure, comprising the steps of:
forming a silicon-on-insulator (SOI) structure having a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX;
anisotropically etching the SOI structure to form a trench through the silicon layer, through the BOX, and through a depth D of the silicon substrate, wherein D≧0;
forming insulative spacers on sidewalls of the trench; and
growing an epitaxial layer of silicon or silicon-germanium alloy in the trench from a bottom of the trench to a height at or above the, silicon layer, wherein the insulative spacers provide electrical insulation between the silicon layer outside the trench and the epitaxial layer.
The present invention provides an electronic structure, comprising:
a silicon-on-insulator (SOI) structure having a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX;
a trench through the silicon layer, through the BOX, and through a depth D of the silicon substrate, wherein D≧0;
insulative spacers on sidewalls of the trench; and
an epitaxial layer of silicon or silicon-germanium alloy in the trench from a bottom of the trench to a height at or above, a top surface of the silicon layer, wherein the insulative spacers provide electrical insulation between the silicon layer outside the trench and the epitaxial layer.
The present invention provides a method and structure for having an epitaxial silicon layer in a trench that is within a SOI layer, wherein the epitaxial layer includes one or more electronic devices, and wherein the SOI layer outside the trench includes one or more electronic devices.
The present invention provides a method and structure for coupling a DRAM cell or a bipolar device to a SOI layer without having a significant degradation of the DRAM capacitor charge retention time.


REFERENCES:
patent: 5366923 (1994-11-01), Beyer et al.
patent: 5481126 (1996-01-01), Subramaniam et al.
patent: 5504027 (1996-04-01), Jeong et al.
patent: 6287930 (2001-09-01), Park
patent: 6429099 (2002-08-01), Christensen et al.

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