SOI electrostatic discharge protection circuit

Details SOI electrostatic discharge protection circuit SOI electrostatic discharge protection circuit

2000-07-24

2002-12-17

Patel, Rajnikant B. (Department: 2838)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C327S306000, C330S277000

Reexamination Certificate

active

06496341

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no.89113939, filed Jul. 13, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit. More particularly, the present invention relates to a silicon-on-insulator (SOI) electrostatic discharge protection circuit (SOI ESD) having a substrate capable of triggering the opening of a bipolar junction transistor so that performance of the ESD protection circuit is improved.
2. Description of Related Art
Electrostatic discharge during manufacture and post-manufacture transportation is a leading cause of damage to integrated circuits (IC) such as dynamic random access memory (DRAM) and static random access memory (SRAM). For example, a person walking on a carpet in a high relative humidity environment can generate several hundred to several thousand volts of static electricity. Under exceptionally dry conditions, a charge of up to ten thousand volts is possible. When the charged body makes contact with a silicon chip, static electricity may discharge causing irreparable damage to the chip. To reduce damage to the chip due to electrostatic discharge, hard-wired electrostatic discharge circuits are often provided. In other words, an on-chip electrostatic discharge protection circuit is formed between the internal circuit and each bonding pad.
In general, thickness of the gate oxide layer increases with the degree of integration. As circuit devices continue to miniaturize, breakdown voltage of the gate oxide layer is fast approaching or even lower than the source/drain junction breakdown voltage. Under such circumstances, performance of the original ESD protection circuit will be greatly compromised. In addition, most internal circuits are designed according to the minimum design rules. The minimum design rules are often prescribed without due regard for combating a large transient current (for example, sufficient space must be set aside between contact and edge of a diffusion region and between contact and edge of a gate). Hence, silicon chips are more vulnerable to electrostatic damage if the level of integration is high. In fact, electrostatic discharge has become one of the major problems in deep-submicron integrated circuitry. Consequently, means of improving the performance of ESD protection circuit is currently high on the list of innovations in the semiconductor industry.
Silicon-on-insulator (SOI) is a widely used technology for forming integrated circuits. Compared with devices formed on a bulk wafer, devices formed on an SOI composite layer have better functional properties. For example, SOI devices consume little power and have a low threshold operating voltage. The functional properties of devices formed on the bulk wafer are critically affected by the formation of inherent parasitic capacitance at the junctions of silicon devices. However, silicon devices of the SOI type are formed above an insulator. Hence, inherent parasitic capacitance is mostly removed. Due to the considerable reduction of parasitic capacitance, devices fabricated according to SOI technology consume less power and have a higher operating speed at a pre-defined device dimension.
In general, silicon-on-insulator (SOI) technology is characterized by the formation of an insulation layer between a bulk wafer and a top silicon layer. All the devices are formed on the top silicon layer. Arranging silicon devices on top of an insulation layer prevents latch-up of CMOS, which reduces the possibility of soft error associated with MOS and increases the operating speed of the circuits.
These benefits notwithstanding, the conventional SOI ESD protection circuit has heat dissipation problems. Hence, the performance of ESD protection circuit is usually low. Although inserting a diode string between the VDD and the VSS terminal is able to raise ESD performance and robustness, the additional diode string occupies considerable surface area.
FIG. 1
is the circuit diagram of a conventional SOI ESD protection circuit. As shown in
FIG. 1
, the SOI ESD protection circuit
10
is positioned between a bonding pad
12
and an input buffer
14
. The protection circuit
10
consists of a first diode
16
and a second diode
18
and an NMOS transistor
20
. The input terminal of the first diode
16
is connected to the bonding pad
12
and the output terminal of the first diode
16
is connected to a voltage source VDD. The input terminal of the second diode
18
is connected to an earth voltage VSS and the output terminal of the second diode
18
is connected to the bonding pad
12
. The source terminal of the NMOS transistor
20
is connected to the source voltage VDD. The gate terminal and the drain terminal of the NMOS transistor
20
are connected to the earth voltage VSS. In addition, the output terminal of the input buffer
14
is coupled to the internal circuit (not shown) inside the chip. The input buffer
14
consist of an NMOS transistor
22
and a PMOS transistor
24
that are serially connected together.
The circuit in
FIG. 1
can be transformed into the one shown in FIG.
2
. In
FIG. 2
, a diode string
26
replaces the NMOS transistor
20
in FIG.
1
. The diode string
26
consists of a plurality of serially connected diodes. The input terminal of the diode string
26
is coupled to the voltage source VDD and the output terminal of the diode string
26
is coupled to the earth voltage VSS.
In the SOI ESD circuit structures shown in
FIGS. 1 and 2
, the gated NMOS transistor
20
and the diode string
26
are respectively used between VDD and VSS. In general, if a gated NMOS transistor such as the one shown in
FIG. 1
is used, problems related to heat diffusion of the SOI substrate often lead to a drop in robustness of the ESD protection circuit. This problem can be mitigated, but at the expense of additional surface area. Similarly, if a diode string such as the one shown in
FIG. 2
is used, then the diode string must contain many diodes to prevent current leakage. Hence, this method also requires consumes more surface area.
SUMMARY OF THE INVENTION
Accordingly, one objective of the present invention is to provide a silicon-on-insulator (SOI) electrostatic discharge (ESD) protection circuit between a bonding pad and an input buffer. The SOI ESD protection circuit includes two diodes, two NMOS transistors and two PMOS transistors. The input terminal of the first diode is coupled to the bonding pad while the output terminal is coupled to a voltage source. The input terminal of the second diode is coupled to an earth voltage while the output terminal is coupled to the bonding pad. Both the source terminal and the gate terminal of the first NMOS transistor are coupled to the earth voltage. The drain terminal of the first NMOS transistor is coupled to the voltage source. Both the source and the gate terminal of the second NMOS transistor are coupled to the earth voltage. Both the source and the gate terminal of the first PMOS transistor are coupled to the voltage source. The drain terminal of the first PMOS transistor is coupled to the substrate of the first NMOS transistor. Both the source terminal and the gate terminal of the second PMOS transistor are coupled to the voltage source. The drain terminal of the second PMOS transistor is coupled to the earth voltage. The substrate of the second PMOS transistor is coupled to the drain terminal of the second NMOS transistor.
The SOI ESD protection circuit of this invention is capable of boosting ESD protection performance and robustness. A positive stress relative to the earth voltage or a negative stress relative to the voltage source is able to trigger the parasitic bipolar junction transistor inside the SOI ESD protection circuit into an open state early on. Hence, the electrostatic stress can be discharged to the earth or the voltage source through the triggering action at the junction between the substrate and the source region of the first NMOS transistor or the second

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