SOI CMOS device with body to gate connection

Details SOI CMOS device with body to gate connection SOI CMOS device with body to gate connection

2001-04-18

2003-12-30

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Charge transfer device

Reexamination Certificate

active

06670655

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the data processing field, and more particularly, relates to a silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) field effect transistor (FET) devices with a body of the SOI FET device connected to the gate of the SOI FET device.
DESCRIPTION OF THE RELATED ART
Silicon-on-insulator (SOI) technology is an enhanced silicon technology currently being utilized to increase the performance of digital logic circuits. Utilizing SOI technology designers can increase the speed of digital logic integrated circuits while reducing their overall power consumption. These advances in technology will lead to the development of more complex and faster computer integrated circuits that operate with less power. Silicon-on-insulator (SOI) technology is also being utilized analog circuits.
Maintaining acceptable body contact resistance in SOI FET devices results in a process that raises the device threshold voltage (Vth) in the SOI FET devices. The raised device threshold voltage Vth causes supply voltage headroom problems.
As SOI technology progresses, the body contact resistance for low and normal Vth devices is increasing to the point that it is not useable because of the 1 Giga-ohm or greater resistance due to the thinning depth and lower dopant concentration of the channel of the SOI FET device. The body contact resistance can be lowered to an acceptable level for higher Vth devices. However, theses devices are difficult to use because the higher Vth causes headroom problems in analog circuits with stacked devices and DC currents. Body contacts are necessary in analog circuits due to matching requirements.
A need exists for a mechanism to maintain acceptable body contact resistance in SOI FET devices without unacceptably raising the device threshold voltage Vth in the SOI FET devices.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) field effect transistor (FET) devices with a body contact without unacceptably raising the effective device threshold voltage Vth in the SOI FET devices. Other important objects of the present invention are to provide such SOI FET devices substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a method and apparatus are provided for implementing a body contact in a silicon-on-insulator field effect transistor device. A SOI field effect transistor is provided having a body contact having a predefined resistance that provides a higher device threshold voltage in the SOI FET device. A body of the SOI field effect transistor is connected to the gate of the SOI field effect transistor. The body gate connection of the SOI field effect transistor effectively lowers the device threshold voltage due to body bias effect.
In accordance with features of the invention, the SOI field effect transistor with a body connected to the gate of the SOI field effect transistor is used in circuits having stacked devices and DC currents. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor also is used in analog circuits with device matching requirements and in circuits having a low voltage power supply.


REFERENCES:
patent: 5559368 (1996-09-01), Hu et al.
patent: 6326666 (2001-12-01), Bernstein et al.
patent: 6369994 (2002-04-01), Voldman
patent: 6459106 (2002-10-01), Bryant et al.

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