Software verification apparatus

Details Software verification apparatus Software verification apparatus

1989-03-30

1991-06-04

Smith, Jerry

Excavating

371 251, G06F 1100

Patent

active

050220284

ABSTRACT:
An apparatus for verification of target software loaded in a target computer. The apparatus includes communication and monitoring circuits inserted in the target computer and in a host computer which is programmed to direct operation of target software tests through the communication and monitoring circuits. The communication and monitoring circuits transmit external stimuli to the target software in a non-intrusive manner by, for example, keyboard simulation. The communication and monitoring circuits also capture target software output data for comparison with reference data stored in the host computer. Both of these operations are carried out in a non-intrusive manner in hardware, (the communication and monitoring circuits). The external stimuli including test instructions may be either recorded in a manual recording session or may be generated in the host computer. Similarly, the target software output reference data may be either generated in the host computer or recorded in a manual session. The apparatus is particularly suitable for regression testing and enables a user to detect faults at any stage of software development irrespective of how many updates are involved.

REFERENCES:
patent: 4696003 (1987-09-01), Kerr
patent: 4899306 (1990-02-01), Greer

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