Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing
Reexamination Certificate
2011-04-19
2011-04-19
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Reexamination Certificate
active
07930659
ABSTRACT:
A system and method is disclosed for formal verification of software programs that advantageously improves performance of an abstraction-refinement loop in the verification system.
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Ganai Malay
Gupta Aarti
Ivancic Franjo
Jain Himanshu
Brosemer Jeffery J.
Chiang Jack
Kolodka Joseph
NEC Laboratories America, Inc.
Parihar Suchin
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