Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system
Reexamination Certificate
1999-07-16
2001-08-07
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
C703S014000, C703S015000, C703S021000, C703S022000
Reexamination Certificate
active
06272451
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates filed programmable system level integrated circuits (FPSLIC), and more particularly to a method and system for co-verifying a hardware simulation and a software simulation of a FPSLIC device.
DESCRIPTION OF THE RELEVANT ART
System level integration (SLI) is rapidly becoming the preferred way to implement electronic designs. Integrating all the system functionality in a system-level integrated circuit (IC) increases performance, reduces power consumption, cuts unit production costs and allows smaller products. These are particularly important benefits in telecommunications, multimedia and networking applications.
A “system” consists of three main building blocks: a processor, memory and logic. Usually, the processor is used for control flow logic, the memory is used for program and data storage and the logic is used for datapath logic. A true system-level solution must contain all three elements.
The ASIC Solution
Until now, system level integration has been implemented in cell-based or masked application specific integrated circuits (ASICs), because these were the only solution available with Unfortunately, ASICs have high non-recurring engineering (NRE) costs, long lead times and significant minimum order quantities. As a result, system level ASIC implementations have been accessible only to the highest volume designs with relatively long product life cycles. Minimum volume requirements for system-level ASIC devices currently are often more than $
5
00K per design per year. Designs with short product life cycles, low to medium volumes, time to market pressures or rapidly evolving standards can not afford the lengthy development cycle, risk and high NRE charges associated with an ASIC solution.
Even when the volume/dollar criteria are met for an ASIC solution, any change in the design to correct an error or improve it leaves the developer with a large inventory of possibly useless parts and another lengthy ASIC design cycle. This is particularly problematic for rapidly evolving designs such as those in telecommunications, networking and multimedia. For these and other designs a programmable solution is preferable because the design can be changed at will both during development and in the field. ASIC solutions are not an option for these designs.
A substantial number of these rapidly evolving designs are implemented in a combination of programmable logic, discrete standard products (microcontrollers, memories) and Application LAW OFFICES Specific Standard Products (ASSPs), such as T1 Interface, ATM, 10/100 PHY, and Video/Audio Codecs. Although this approach offers the flexibility to evolve designs rapidly it does not offer the performance, power, space and reliability advantages of a monolithic system level integrated circuit. A single-chip, programmable solution is clearly the preferable alternative.
Multiple Approaches to Programmable System Level Integration
Field programmable gate array (FPGA) and other IC vendors have developed a variety of approaches to providing programmable system level integration. These include “pure play” high-density FPGAs and hybrid devices that combine both FPGA and fixed logic functionality.
The most widely promoted means of achieving programmable SLI today are Xilinx's Virtex® and Altera's APEX® FPGA families that boast as many as a million gates. Although industry analysts believe these gate counts may be substantially overstated, these devices are still large enough to support system level integration of designs that might otherwise go into a masked- or cell-based ASIC. FPGAs now compete with masked-ASICs in terms of both density, and in the case of low density FPGAs, price. High density FPGAs are being proposed as a programmable, single-chip solution for system level integration. Although the programmability of the large FPGAs is very attractive, they have some significant drawbacks:
Although deep sub-micron process technologies have reduced the prices of low and medium density FPGA so that in many cases FPGA prices are on a par with those of ASICs, high gate count devices are extremely expensive. For example, Xilinx's million gate Vertex XCV1000 device currently sells for $4,298.00 each. The extremely high prices of these devices limits their use to ASIC prototyping and production runs of a handful of very high priced products. When one considers that a masked-ASIC of comparable density cost about $50, these large FPGAs are out of reach for most volume designs/applications.
Although FPGA devices can cut the ASIC development cycle in half, the complexity of large FPGAs mandates a significant design and development process for system level designs. Today ‘time-to-market’ is the difference between success and failure of a product. Designing a million gates of FPGA logic takes a great deal of time. Frequently intellectual property (IP) cores are used to reduce the design cycle. However, integrating vendor supplied soft IP into a design is in itself often a cumbersome and time-consuming process.
Simulation is another problem with large FPGAs. HDL simulations are notoriously slow for simulating large designs, especially ones using complex soft IP cores. Simulating a one million gate FPGA design can take so long that many designers simulate less thoroughly than is desirable or not at all. The result is that these designs are more likely to have undiscovered bugs that extend the debug cycle, further delaying product introductions.
This problem is further amplified if a microcontroller soft IP core is being used in a large FPGA design. Conventional MCU design methodologies are not available to the designer in the large FPGA based design flow. Typically, microcontroller designers have code development and debugging tools that are used to debug the microcode. These tools are often not available for soft IP cores used on a large FPGA, so code development and debugging are problematic if not impossible.
Furthermore, because of the lack of code development and debugging tools available for processor cores, the integration and debug of the microcontroller portion of a these designs is extremely difficult. Similar arguments can easily be made for timing analysis on system-level FPGA designs.
One solution to the complexity of designing system-level FPGAs is to use “drop-in” soft intellectual property cores. Memory, logic and a limited number of processor IP cores can be purchased from third party vendors and dropped into large FPGAs. However, soft IP cores are expensive, difficult to integrate in the design, and tend to be silicon inefficient. The difficulty of integrating IP cores from different third-party vendors can significantly extend the product development cycle. For example, an 8051 core for the Xilinx Virtex, supplied by Dolphin in France, costs over $10,000 to license and uses 1010 CLBs or 16.4% of a XCV1000. At a list price of $4,298 for each XCV1000, the silicon cost of the 8051 core is $704, excluding the cost of the core itself.
“The Flip-8051 core forms the heart of a family of processors that include lower performance options as well as microcontroller configurations that include peripherals such as timers and serial interfaces. Pricing starts as low as $10,000 for an EDIF format for Virtex FPGAs. Other design file formats are available. A VHDL source-code version is available with a test bench at extra cost.
There are additional design problems associated with building the interfaces between the various cores and correcting timing problems. Studies have shown that up to one half of the typical design project is spent in the integration and test phase, which in reality becomes an exercise in correcting the accumulation of errors from the front end of the design cycle. These problems are magnified when multi-site, multi-engineer development teams work on large FPGA-based systems. The errors often reach all the way back to the specification and partitioning phase, where ambiguities in the hardware/software interface were introduced and then amplified during the hardware/softwa
Dasari Ajithkumar Venkata
Mason Martin Thomas
McConnell David Andrew
Atmel Corporation
Chartered David Newman
Knox Lonnie A.
Teska Kevin J.
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