Software reconfigurable target I/O in a circuit emulation system

Details Software reconfigurable target I/O in a circuit emulation system Software reconfigurable target I/O in a circuit emulation system

1997-03-03

1999-10-05

Teska, Kevin J.

G06F 9455

Patent

active

059637366

ABSTRACT:
A time-sliced hardware-based emulator including at least one of: programmable I/O assignment; programmable levels of DC voltage; programmable pull-up or pull-down resistors in the emulator on a pin-by pin basis; programmable forcing and/or disabling of value output from the emulator on each pin; programmable clocking; and programmable sample modes. An emulator is connected to a target system via a Pod System Interface (PSI), a specially designed cable, and a Pod User Interface (PUI). For data traveling from the emulator to the target system, each PSI receives up to 128 bits of data from the emulator. The cable, however, is only 32 bits wide. Therefore, the emulator multiplexes the data sent over the cable, sending eight interleaved groups of 32 bits to the PSI in accordance with a fast clock signal. Each PUI receives the groups of 32 bits from the PSI and sends them to the target system in accordance with control signals from the emulator. For data traveling from the target system to the emulator, each PUI receives up to 128 bits of data from the target system. Each PUI sends four groups of 32 bits in accordance with a fast clock signal. Each PSI receives the groups of 32 bits and holds them in an internal register, sending the received bits to the emulator under control of the emulator.

REFERENCES:
patent: 5321828 (1994-06-01), Phillips et al.
patent: 5721880 (1998-02-01), McNeill, Jr. et al.
patent: 5743748 (1998-04-01), Takahata et al.
patent: 5761484 (1998-06-01), Agarawal et al.
patent: 5774695 (1998-06-01), Autrey et al.
patent: 5781759 (1998-07-01), Kashiwabara

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