Software programmable delay circuit

Details Software programmable delay circuit Software programmable delay circuit

2000-12-29

2003-02-11

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S277000

Reexamination Certificate

active

06518811

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to delay circuits and more particularly to providing a programmable digital delay circuit in a programmable device that is routing independent.
2. Description of the Related Art.
The first generations of fiber-optic systems in the public telephone network used proprietary architectures, equipment, line codes, multiplexing formats, and maintenance procedures. These transmission systems were asynchronous, with each terminal or hub in the network running on a different clock. In digital transmission, a clock refers to a series of repetitive pulses that keep the bit rate of data constant and indicate the location of ones and zeroes in a data stream. Since the clocks in the first generation systems were not synchronized, large variations occurred in the clock rate and thus the signal bit rate.
The synchronous optical network (SONET) standard was developed to provide a synchronous optical system that enables the interconnection of equipment from different suppliers without causing large variations in the clock rate and the signal bit rate. The SONET standard defines a technology for carrying many signals of different capacities through a synchronous, flexible, optical hierarchy. SONET defines a set of synchronous signals, including optical carrier (OC) levels and electrically equivalent synchronous transport signals (STSs) for the fiber-optic-based transmission hierarchy. A similar standard to SONET is the Synchronous Digital Hierarchy (SDH) which is the optical fiber standard predominantly used in Europe. There are only minor differences between the two standards. Accordingly, hereinafter any reference to the term SONET refers to both SDH and SONET networks, unless otherwise noted.
In a set of synchronous signals, digital transitions occur at exactly the same rate. There can, however, be a phase difference between the transitions of the two signals, which must lie within specified limits. The phase differences can be due to propagation time delays or jitter introduced into the transmission network. In the synchronous network defined by SONET, all clocks are traceable to one primary reference clock (PRC), also referred to as a Stratum 1 atomic clock. The accuracy of the PRC is better than +−1 in 10
11
.
SONET utilizes a byte-interleaved multiplexing scheme. Mulitplexing enables one physical medium to carry multiple signals. Byte-interleaving simplifies multiplexing and offers end-to-end network management. Each STS is transmitted on a link at regular time intervals (for example, 125 microseconds) and grouped into frames. See Bellcore Generic Requirements document GR-253-CORE (Issue 2, December 1995), hereinafter referred to as “SONET Specification,” and incorporated herein by reference for all purposes. The first step in the SONET multiplexing process involves the generation of the lowest level or base signal. In SONET, this base signal is referred to as synchronous transport signal—level 1, or simply STS-1, which operates at 51.84 Mbps. Higher-level signals are integer multiples of STS-1, creating the family of STS-N signals in Table 1. An STS-N signal is composed of N byte-interleaved STS-1 signals. Table 1 also includes the optical counterpart for each STS-N signal, designated optical carrier level N (OC-N).
TABLE 1
SIGNAL
BIT RATE (Mbps)
STS-1, OC-1
51.840
STS-3, OC-3
155.520
STS-12, OC-12
622.080
STS-48, OC-48
2,488.320
STS-192, OC-192
9,953.280
NOTE:
Mbps = Mega bits per second
STS = synchronous transport signal
OC = optical carrier
SONET organizes STS data streams into frames, consisting of transport overhead and a synchronous payload envelope. The overhead consists of information that allows the network to operate and allow communications between a network controller and nodes. The transport overhead includes framing information and pointers, and performance monitoring, communications and maintenance information. The synchronous payload envelope is the data to be transported throughout the network, from node to node until the data reaches its destination.
SONET utilizes pointers to accommodate differences in the reference source frequencies and phase wander and to prevent frequency differences during synchronization failures. Adjustments to the pointers compensate for frequency and phase variations. The use of pointers avoids the delays and loss of data associated with the transmission of large amounts of data. A pointer is an offset value that points to the byte where the payload begins in the frame. The pointer allows the payload to be separated from the transport overhead. If there are any frequency or phase variations between the frame and the associated payload, the pointer value will be increased or decreased accordingly to maintain synchronization. When there is a difference in phase or frequency, the pointer value is adjusted. To accomplish this, a process known as byte stuffing is used. In other words, the payload pointer indicates where in the frame the payload starts, and the byte-stuffing allows dynamic alignment of the payload in case the payload slips in time.
Routers, cross-connect systems, and other network nodes are commonly employed in the telecommunication network synchronization hierarchy. The network is organized with a master-slave relationship with clocks of the higher level nodes feeding timing signals to clocks of the lower-level nodes. All nodes can be traced up to the primary reference source, a Stratum 1 atomic clock with extremely high stability and accuracy. The internal clock of a SONET hub derives the hub's timing signal from a Building Integrated Timing Supply (BITS) clock used by switching systems and other equipment. The hub serves as a master for other SONET nodes, providing timing on the hubs' outgoing OC-N signal. Current standards specify that a SONET network must be able to derive the internal timing from a Stratum 3 or higher clock. A SONET optical cross connect accepts various optical carrier rates, accesses the STS-1 signals, and switches at this level.
A common feature of a telecommunication system node is the redundancy built into the architecture. Redundancy refers to providing a duplicate set of circuitry that functions as a backup system in case of a failure. At any given time, one set of circuitry is designated as active while the other is designated standby. When a failure occurs in a portion of the active circuitry, the corresponding standby circuitry is switched to active and the active circuitry is switched to standby, allowing the circuitry to be repaired without bringing the system into a non-operational state. In addition, the redundancy in the architecture provides for other activities, such as routine maintenance and circuit or software upgrades to occur while allowing the system to continue functioning. Although circuitry is designated as either active or standby, both circuits can be fully operational. The outputs of the redundant circuits are monitored and compared for performance and failures.
In a SONET hub, clocks are derived from the BITS clock and then distributed throughout the hub. Processors, electrical components, control signals, etc. need clock signals to run properly. To provide clock inputs to all of these circuits, the original clock signal needs to be duplicated, typically via clock trees utilizing layers of clock buffers. Clock buffering, as well as loading, routing, temperature, and voltage differences lead to phase misalignment between the derived clock signals. Routing, duplication and selection of clock signals due to the redundancy of the architecture further increases the phase difference between clock signals.
Unless compensated for, the clock operating the active circuitry can have a large phase difference from the clock operating the standby circuitry. In some designs, the phase difference does not affect the operation of the system except when switching between active and standby circuitry. The phase difference, if not corrected, can cause data loss.

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