Software invalidation in a multiple level, multiple cache system

Details Software invalidation in a multiple level, multiple cache system Software invalidation in a multiple level, multiple cache system

1995-06-07

1997-12-16

Lim, Krisna

395449, 39542102, G06F 1200

Patent

active

056995512

ABSTRACT:
A method of invalidating a line in a designated cache in each level of a multiple level, multiple cache memory system. Each line of the cache memory system includes a tag field, a data field, and a bit indicative of the validity of the line. The method provides a software invalidate instruction which bypasses any address translation mechanism. Included in the software invalidate instruction is a first field to identify within which multiple cache the line is to be avoided. A target address is generated to index each level of the cache memory system. The state of the bit is changed in accordance with the address and the invalidate instruction.

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