Patent
1996-05-15
1998-07-28
Coleman, Eric
395379, G06F 700
Patent
active
057873020
ABSTRACT:
Software creates a compressed instruction format for a VLIW processor which allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.
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Ang Michael
Hampapuram Hari
Jacobs Eino
Lee Yen C.
Barschall Anne E.
Coleman Eric
Philips Electronic North America Corporation
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