Software configurable digital clock generator

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control

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327115, 377 47, H03B 1900

Patent

active

057195102

ABSTRACT:
The clock generator generates an output clock signal of known frequency from an internally generated high frequency signal of unknown frequency and from a low frequency input signal of known frequency. To this end, the clock multiplier first determines the frequency of the internal clock signal from a comparison with the input clock signal. In one arrangement, the frequency of the internal signal is determined by counting a number of clock transitions occurring during the internal signal within one period of the input clock signal. Once the frequency of the internal signal has been determined, the clock multiplier generates an output clock signal based upon the internal clock signal but adjusted in accordance with the newly determined frequency of the internal clock signal. In one arrangement, the clock multiplier employs a programmable divider. A software control unit calculates a divide factor for use by the programmable divider based upon the period of the input signal, the count of transitions, and the desired period for the output signal. The internal signal is then routed through the programmable divider to divide the signal by an amount sufficient to produce an output signal having a period approximately equal to the desired output period. In one specific arrangement, the internal signal is generated by a ring oscillator which produces an internal signal having a frequency of, for example, 300 megahertz (MHz) to 500 MHz. The programmable divider divides the internal signal by a divide factor between 6 and 10 to yield an output frequency of about 50 MHz. The clock multiplier also includes a mechanism for determining whether the actual frequency of the output signal remains within an acceptable range of frequencies and for reprogramming the programmable divider, if necessary, to reset the output frequency to within the acceptable range of frequencies. Method and apparatus embodiments of the invention are described.

REFERENCES:
patent: 3970954 (1976-07-01), Even
patent: 5398007 (1995-03-01), Yamazaki et al.

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