Software-based technique for improving the effectiveness of...

Electrical computers and digital processing systems: processing – Instruction fetching – Prefetching

Reexamination Certificate

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Reexamination Certificate

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07373482

ABSTRACT:
One embodiment of the present invention provides a system that improves the effectiveness of prefetching during execution of instructions in scout mode. During operation, the system executes program instructions in a normal-execution mode. Upon encountering a condition which causes the processor to enter scout mode, the system performs a checkpoint and commences execution of instructions in scout mode, wherein the instructions are speculatively executed to prefetch future memory operations, but wherein results are not committed to the architectural state of a processor. During execution of a load instruction during scout mode, if the load instruction is a special load instruction and if the load instruction causes a lower-level cache miss, the system waits for data to be returned from a higher-level cache before resuming execution of subsequent instructions in scout mode, instead of disregarding the result of the load instruction and immediately resuming execution in scout mode. In this way, the data returned from the higher-level cache can help in generating addresses for subsequent prefetches during scout mode.

REFERENCES:
patent: 5689712 (1997-11-01), Heisch
patent: 5768500 (1998-06-01), Agrawal et al.
patent: 6516462 (2003-02-01), Okunev et al.
patent: 2005/0251666 (2005-11-01), Chaudhry et al.
Mutlu et al.; Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors; Feb. 2003; IEEE Computer Society; HPCA '03; pp. 129-140.
Roth et al.; Dependence Based Prefetching for Linked Data Structures; 1998; ACM Press; ASPLOS '98 pp. 115-126.
Collins et al.; Speculative Precomputation: Long-range Prefetching of Delinquent Loads; 2001; ACM Press; ISCA '01; pp. 14-25.

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