Patent
1992-10-06
1996-02-20
Lane, Jack A.
G06F 1210
Patent
active
054936608
ABSTRACT:
The present invention provides a software-assisted hardware TLB miss-handler which is designed to reduce the TLB miss penalty while being low cost to implement and requiring little chip area or complexity. When a TLB miss occurs, the HW TLB miss handler of the present invention computes a physical address of a page table entry located in a special hardware-visible table based on a missing virtual address. It accesses the page table entry and checks for a correct translation and status information. If correct, a physical page address and protection information of the page table entry are inserted into the TLB. The original virtual address is re-translated and normal program execution continues. If the correct translation and status are not found, the HW TLB miss-handler will not insert the entry and will trap to a more sophisticated SW TLB miss handler. A pointer to the page table entry is passed to the SW TLB miss handler so that the page table address need not be recomputed. Thus, the HW TLB miss-handler of the present invention services the simplest and most common TLB misses very quickly, reducing the overall TLB miss penalty. The slower SW TLB miss handler services the more complex and less common TLB misses and provides flexibility in the virtual memory management system.
REFERENCES:
patent: 4774653 (1988-09-01), James
patent: 5060137 (1991-10-01), Bryg et al.
Buckley Michael A.
DeLano Eric R.
Weir Duncan C.
Hewlett--Packard Company
Lane Jack A.
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