Active solid-state devices (e.g. – transistors – solid-state diode – With specified impurity concentration gradient – With high resistivity
Reexamination Certificate
2000-06-26
2004-05-18
Nadav, Ori (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
With specified impurity concentration gradient
With high resistivity
C257S655000, C257S927000
Reexamination Certificate
active
06737731
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of electronic devices, and, more particularly, to power diodes.
BACKGROUND OF THE INVENTION
Diodes are used in a variety of circuits to either restrict or permit the flow of current within the circuit depending upon the voltage which is applied across the diode. That is, the voltage will either cause the diode to become forward-biased, at which point the current will flow through the diode, or reverse-biased, at which point current is restricted from flowing through the diode.
Diodes such as the P-i-N (positive-intrinsic-negative) diodes are widely used in high voltage applications, such as power factor correction circuits, for example. When such a diode transitions suddenly from a forward-biased state to a reversed-biased state caused by a large voltage swing, the diode must undergo a period of reverse recovery. During the forward-biased state the i region of the diode contains a large concentration of minority carriers. This concentration must be removed from the i region before the current flow can be limited to substantially zero. Accordingly, after being switched to, a reverse-biased state a reverse recovery current (Irr) will increase in magnitude until the excess carrier concentration at the P-N junction has dropped below the background concentration at a time t (i.e., the time when the current reaches a negative peak), at which point reverse recovery can begin.
If the minority carrier concentration becomes too large, it is possible that the Irr may increase to the point at which the circuit is damaged. Accordingly, it is desirable to have a low Irr to avoid this disadvantage. Yet, reducing the Irr results in an increase in the forward voltage drop (Vf) of the diode as well a decrease in the softness of the recovery waveform, both of which are undesirable. The softness of the recovery waveform corresponds to the slope of the Irr (i.e., dIrr/dt) as it tends toward zero after the time t. The steeper the slope, the less “soft” the recovery waveform and the greater the chance that ringing will result. Ringing is caused when the current overshoots or oscillates back and forth about zero during the reverse recovery period because the current increases and decreases too quickly due to circuit parasitics.
Accordingly, there is a need for a power diode that provides for a relatively low Irr value while maintaining a low Vf and soft recovery characteristics. Various attempts have been made in the prior art to create such diodes. One example is U.S. Pat. No. 4,594,602 to Iimura et al. entitled “High Speed Diode.” The diode has a PNN<+>structure which is intended to provide high speed switching characteristics along with a soft reverse recovery and low forward voltage drop. However, the structure of this diode may not provide an adequate balance of reduced Irr and increased softness in certain applications.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the invention to provide a semiconductor diode having relatively low Irr and Vf values and further exhibiting soft recovery characteristics.
This and other objects, features, and advantages in accordance with the present invention are provided by a semiconductor diode including a more highly doped base layer between the intrinsic layer and the base. More particularly, the diode may comprise a first semiconductor layer that includes a dopant having a first conductivity type and a second semiconductor layer adjacent the first semiconductor layer that includes a dopant having the first conductivity type and having a dopant concentration less than a dopant concentration of the first semiconductor layer. Additionally, a third semiconductor layer maybe adjacent the second semiconductor layer and includes a dopant having the first conductivity type and having a dopant concentration greater than the dopant concentration of the second semiconductor layer. This third layer may be considered as providing the more highly doped base layer or region. A fourth semiconductor layer maybe adjacent the third semiconductor layer and include a dopant of a second conductivity type. Respective contacts are connected to the first and fourth semiconductor layers. The diode has a reduced Irr compared to prior art diodes yet still provides a low Vf and soft recovery characteristics.
The semiconductor diode may further include an intermediate semiconductor layer between the first semiconductor layer and the second semiconductor layer. The intermediate semiconductor layer has a dopant concentration between the dopant concentrations of the first and second semiconductor layers. Additionally, the fourth semiconductor layer may be surrounded by the third semiconductor layer.
By way of example, the dopant concentrations and thicknesses of the semiconductor layers may be as follows: for the first semiconductor layer, a dopant concentration in a range of about 1×10
18
to 1×10
19
cm
−3
and a thickness in a range of about 100 to 400 &mgr;m; a for the intermediate semiconductor layer, a dopant concentration in a range of about 2.5×10
14
to 1.3×10
15
cm
−3
and a thickness in a range of about 8 to 35 &mgr;m; for the second semiconductor layer, a dopant concentration in a range of about 6×10
13
to 6×14
14
cm
−3
and a thickness in a range of about 7 to 70 &mgr;m; for the third semiconductor layer, a dopant concentration in a range of about 1×10
14
to 1×10
16
cm
−3
and a thickness in a range of about 4 to 6 &mgr;m; and for the fourth semiconductor layer, a dopant concentration in a range of less than about 1×10
17
cm
−3
and a thickness in a range of about 2 to 4 &mgr;m.
In addition, the first conductivity type is preferably N type and the second conductivity type is preferably P type. Another aspect of the invention relates to doping-the fourth semiconductor region with relatively low concentrations compared to those found in prior art devices. Accordingly, the excess carrier concentration at the P-N junction between the third and fourth semiconductor layers is held to a lower level, thus resulting in a reduced Irr at the time t (hereafter “Irrm”). Increasing the doping concentration of the third semiconductor layer further reduces the carrier concentration at the P-N junction, providing for further reduction in the IrrM. The dopant concentration of the fourth semiconductor layer preferably has a dopant concentration greater than the dopant concentration of the third semiconductor layer. Furthermore, the dopant concentration may be chosen to cause an excess carrier concentration region away from the P-N junction during operation to be higher than in prior art devices, which serves to maintain Vf at low values and produce a soft recovery waveform.
A method according to the invention is for making a semiconductor diode. The method preferably includes providing a semiconductor substrate including a dopant having a first conductivity type. A first epitaxial layer of the first conductivity type is grown adjacent the semiconductor substrate and may have a dopant concentration less than a dopant concentration of the first semiconductor layer. The method may further include doping a first region of the first conductivity type in the first epitaxial layer to a dopant concentration less than the dopant concentration of the first epitaxial layer, and doping a second region of a second conductivity type in the first region. Additionally, respective contacts maybe formed on the semiconductor substrate and the second region.
REFERENCES:
patent: 4228453 (1980-10-01), Pearsall
patent: 4594602 (1986-06-01), Iimura et al.
patent: 4954850 (1990-09-01), Kasahara
patent: 5017950 (1991-05-01), Kasahara
patent: 5032540 (1991-07-01), Follegot
patent: 5323029 (1994-06-01), Nishizawa
patent: 5608244 (1997-03-01), Takahashi
patent: 5773858 (1998-06-01), Schlangenotto et al.
patent: 5811873 (1998-09-01), Soejima
patent: 5977611 (1999-11-01), Sittig et al.
patent: 0103138 (1984-03-01),
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Fairchild Semiconductor Corporation
Nadav Ori
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