Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-12-14
2002-10-22
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185190, C365S185130, C365S185330
Reexamination Certificate
active
06469934
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an optimized soft programming method for flash EEPROM type non-volatile memory cells.
BACKGROUND OF THE INVENTION
As is known, the erasing operation of flash cells takes place by Fowler-Nordheim tunneling, and is carried out by increasing, for a pre-determined time, which is subdivided into one or more erasing pulses, the potential of the bulk regions (bulk erasing), or the potential of the source regions (source erasing) of these cells, as described in R. Bez, D. Cantarelli, G. Ortolani, G. Servalli, C. Villa and M. Dallabora: “A New Erasing Method for a Single-Voltage Long-Endurance Flash Memory,”
IEEE Electron Devices Letters
, Vol. 19, No. 2, February 1998. Since, in NOR type memory architectures, the flash cells belonging to a single memory sector have in common the bulk regions and the source regions, the erasing operation is carried out in parallel on all the flash cells belonging to a single memory sector.
In detail, the bulk erasing operation takes place by supplying one or more erasing pulses of a pre-determined duration, to the cells of an addressed sector. More specifically, for a pre-determined time the bulk region that is common to all the cells in the addressed sector is supplied with a voltage V
B
which increases in a non-linear manner, starting from a minimum potential equivalent to 0V, up to a maximum potential equivalent to 8V (FIG.
1
).
Simultaneously, all the word lines connected to the gate terminals of the cells in the sector addressed are biased to a negative voltage (−8V), whereas all the bit lines connected to the drain terminals of the same cells, and the source terminals, are left floating.
By this means, below the floating gate regions of the cells in the sector addressed, there is created a transverse electrical field with an intensity such as to permit extraction of the electrons which have remained trapped in this floating gate region, after a preceding programming operation. The threshold voltage of these cells is consequently decreased to a pre-determined threshold value.
One of the problems which is encountered most frequently in erasing of memory cells is that after application of the erasing pulses, some memory cells are erased excessively, until a threshold voltage which is too low, or even negative, is obtained. These cells are therefore in a conductive state, even though their respective word lines are biased to ground (depleted cells).
It is known that in a non-volatile memory which has a NOR type configuration, the presence of depleted cells can distort the subsequent reading operation of the memory itself. It is therefore necessary In memories of this type, to follow the erasing operation with a soft programming operation of the depleted cells.
According to a first known solution, this soft programming operation consists of supplying, to a previously addressed cell, one or more soft programming pulses with a pre-determined duration, each of which is followed by a phase of checking the soft programming of the cell itself, similar to the normal programming phase.
Although this first known solution has the advantage of being selective in the soft programming of each individual cell, it has the disadvantage of having to be carried out before the condition of depletion is completely established in the cells that are not addressed. In fact, the efficiency of soft programming of the cell addressed decreases significantly if there are various depleted cells, since in this case, part of the charge that is supplied for soft programming of the cell addressed is lost through the effect of the other depleted cells.
In addition, the erasing algorithm obtained by means of this first known solution is very slow and complex, since the soft programming operation must be carried out on each individual cell.
According to another known solution, the soft programming operation consists of biasing a pre-selected group of cells (hereinafter defined as pre-selected cells) belonging to a memory sector previously erased, such as to produce in these cells an increase in the threshold voltage to above a pre-determined soft programming value, thus eliminating the condition of depletion.
For this purpose, for a pre-determined time, a ramp voltage is applied to the word lines connected to the gate terminals of the pre-selected cells, whereas the remaining word lines in the sector are set to a negative potential which is equivalent to −2V.
Simultaneously, a constant positive potential is applied to the bit lines connected to the drain terminals of the pre-selected cells.
On the other hand, the source terminals and the common bulk region are connected respectively to ground and to a constant negative potential.
Since this known solution uses a high level of parallelism in soft programming of the cells, it has the advantage that it makes the erasing algorithm faster and simpler than the known solution previously described. However, its implementation requires somewhat complex row decoding, and negative voltage generators in order to generate the negative voltage to be applied to the word lines which are not addressed.
In addition, the known solutions previously described do not exclude the possibility that, once the phase of erasing of the addressed sector has been completed, and the corresponding biasing voltages have been applied in order to carry out the soft programming of the same sector, some cells in the sector may still be depleted, partly owing to the variability of behavior of the individual cells.
In this case, the use of the current supplied to the bit lines addressed is not optimal. In fact, if depleted cells are also connected to these bit lines, in addition to the pre-selected cells, part of the current which is available on the bit lines flows into the depleted cells, without however affecting their threshold voltage. This current is therefore wasted for the purposes of soft programming of the cell or of the group of pre-selected cells, thus decreasing the efficiency of soft programming.
SUMMARY OF THE INVENTION
According to the present invention, an optimized soft programming method is provided for non-volatile memory cells. This method is used in a memory having a plurality of cells that are grouped into sectors. The cells that belong to a single sector have gate terminals connected to a plurality of word lines, and drain terminals connected to a plurality of local bit lines. The soft programming method is carried out by selecting at least one local bit line in the sector, and simultaneously selecting all the word lines in the same sector. A corresponding gate voltage is applied to all the word lines, whereas a constant drain voltage, with a pre-determined value is applied to the local bit line.
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de Sandre Guido
Pasotti Marco
Rolandi Pier Luigi
Carlson David V.
Elms Richard
Nguyen Tuan T.
Seed IP Law Group PLLC
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