Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Reexamination Certificate
1999-07-28
2003-12-16
Bayard, Emmanuel (Department: 2631)
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
Reexamination Certificate
active
06665357
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to channel coding for digital communications systems and, more particularly, to a turbo code decoder useful for channel coding and a method for optimizing the performance of a turbo code decoder.
Forward error correction (FEC) is a system of error control for data transmission systems where the receiver is capable of detecting and correcting errors in the “as received” message induced by noise in the transmission channel. FEC is useful in connection with data transmission systems which lack a reverse channel with which retransmission of data can be requested or where retransmission would be difficult because the delay would be excessive or repeated retransmission would be required because of the number of expected errors. For these reasons, FEC has been of particular interest and use in wireless communication and space probe and satellite data transmission systems. FEC relies on channel coding where input message sequences are mapped to code symbol sequences that add redundancy and memory to the data before transmission.
Generally, channel coding utilizes block or convolutional coding to add redundancy to the message bit stream. Block coding breaks the bit stream representing the message into fixed size blocks and independently adds redundant code symbols to each block. Block coding is usually decoded with algebraic techniques. On the other hand, convolutional coding continuously adds redundant symbols to the bit stream based on the contents of the stream. In the convolutional encoder, the bits of the message are shifted serially into and out of a shift register having a number of individual registers. The output code is the result of modulo arithmetic performed on the contents of the shift register and, in some cases, the input bit stream as each successive message symbol or bit is shifted into the register. While bit stream segmentation is not required for convolutional coding, the coded bit stream is typically broken into blocks or frames for other reasons before transmission. Decoding of convolutional codes is accomplished with a heuristic or trial-and-error approach.
Turbo codes are produced by encoders comprising two, or more, parallel, constituent encoders. The constituent encoders are often, but not necessarily, identical convolutional encoders. An interleaver or permuter is attached to the input of one or more of the constituent encoders. The interleaver rearranges the input of the attached constituent encoder in a systematic, pseudo-random manner. As a result, turbo codes comprise two or more (depending on the number of encoders) independently coded symbol streams that refer to the same input information bit stream. Turbo codes are of particular interest because with a relatively simple constituent code and large interleaver their performance can be near the theoretical or Shannon limit of the transmission channel.
Turbo code decoding is an iterative process with the results of a first modular decoder forming part of the input to a second modular decoder and so forth until the required number of iterations is achieved. When the turbo code is composed of two parallel concatenated codes, the modular turbo code decoder comprises two serially connected constituent decoders separated by an interleaver that reorders the output of the first decoder so that it may be used as input to the next decoder. Decoders for turbo codes with more than two parallel constituent codes may take a number of forms. A convolutional encoder is a state machine that codes by tracing a path through a code tree or trellis on the basis of the sequence of input symbols. From the symbols of the “as received,” coded message the convolutional code decoder attempts to retrace the encoder's path through the code tree or trellis outputting the symbols of the decoded message while correcting errors incurred in transmission. One technique for decoding convolutional codes relies on algorithms which retrace the path of “maximum likelihood” through the trellis. One such “maximum likelihood” algorithm used in turbo code decoding is the soft output Viterbi algorithm (SOVA). A constituent decoder applying the SOVA algorithm computes or estimates the “log likelihood ratio,” the logarithm of the ratio of the conditional probabilities of receiving the two outcomes (binary “1” and “0”) given the observed signal value. The output of the constituent decoder is a plurality of signed numbers. The sign expresses the polarity of the decoded message symbol. The magnitude is a “soft” or analog value expressing the probability that the decoded symbol is the same as the original message symbol.
Generally, the turbo code decoder converges on a final decoded symbol sequence with successive iterations and the error rate performance improves until a threshold number of iterations is reached. While the error rate performance of the decoder generally improves with additional iterations, the rate of improvement decreases. Each iteration takes time further delaying completion of decoding. Heretofore, the number of iterations to be performed by a particular turbo code decoder was hard wired into the decoder. Optimizing the number of iterations to be hardwired into the decoder involves compromises in the error rate and latency of the decoder's performance. Further, due to the random nature of noise, “as received” data sequences are unequally corrupted and require different numbers of iterations to achieve the same level of error correction.
What is desired, therefore, is a turbo code decoder and a method of decoding that optimize the performance of the decoder producing a given level of error correction in the fewest number of decoding iterations on the average. Further, it is desired that the operation of the decoder be responsive to the error correcting requirements of each message. Optimizing the decoding process reduces the latency in decoding a message at an acceptable error rate and reduces the cost and complexity of the decoder.
SUMMARY OF THE INVENTION
The present invention overcomes the aforementioned drawbacks of the prior art by providing a method of optimizing the performance of an iterating turbo code decoder having a plurality of constituent decoders comprising the steps of establishing a limit for an output of a constituent decoder; determining the number of decoder outputs approximately equaling the limit for each of successive iterations by the turbo code decoder; and terminating operation of the turbo code decoder when the numbers of the decoder outputs approximately equaling the limit are substantially unchanged for successive iterations. The progress of a turbo code decoder in decoding a message sequence can be monitored by establishing a limit for the output of a constituent decoder and monitoring the number of outputs of equaling or approaching the limit. If the number of outputs approaching the limit or saturating does not change for successive iterations by the turbo code decoder, no progress is being made in decoding the message. Operation of the turbo code decoder can be terminated without loss of data.
A second technique applying the method of optimizing the performance of an iterating turbo code decoder including a plurality of serial constituent decoders comprises establishing a limit for an output of a constituent decoder; determining a first and a second number of the outputs approximately equaling the limit produced by the second serial constituent decoder while performing a first iteration and a second iteration, respectively; determining a third number of the outputs approximately equaling the limit produced by the first serial constituent decoder while performing the second iteration; and terminating operation of the turbo code decoder when the first, second, and third numbers of outputs are substantially equal.
A third technique for applying the method of optimizing the performance of an iterating turbo code decoder including a plurality of serial constituent decoders comprises establishing a limit for an output of a constituent deco
Bayard Emmanuel
Chernoff Vilhauer McClung & Stenzel LLP
Sharp Laboratories of America Inc.
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