Soft error correction technique and system for odd weight row er

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G11C 2900

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056445830

ABSTRACT:
A soft error correction technique and system for an odd weight row error correction code comprising a memory for storing a data word and its associated check bits and a control circuit for reading and inverting the data word and the check bit stored in memory. The system also comprises an inversion circuit for selectively reinverting the check bits. In a specific implementation, the check bit inversion circuit includes a plurality of Exclusive Or gates. A first input of each Exclusive Or gate is connected to receive the check bit from memory and a second input is connected to receive a control bit from a central processing unit via a software accessible control register. The inverted data word and the selectively reinverted check bit are input to an odd weight row error correcting circuit to correct a detected bit error. A method for correcting data errors for an odd weight row error correction system is also provided. The method consists of storing a data word and its associated check bits; reading and inverting the stored data word and check bit; providing a control word; selectively reinverting the stored check bit; and correcting errors in the inverted stored data word using an odd weight row error correction code.

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Kaufman, "Fault-Tolerant Memory with Simple Error Correcting Codes", IBM Tech. Disclosure Bulletin, vol. 26, No. 11, Apr. 1984, pp. 6142-6144.

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