Socket for housing a plurality of integrated circuits

Details Socket for housing a plurality of integrated circuits Socket for housing a plurality of integrated circuits

1980-09-05

1982-12-21

McGlynn, Joseph H.

Geometrical instruments

339112R, H01R 1300

Patent

active

043646204

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention pertains in general to integrated circuits and in particular to the packaging of such circuits.


BACKGROUND ART

There are numerous applications in which it is desirable to include more than one integrated circuit within a single socket. The standard 16K dynamic random access memory (RAM) now commonly in use has a 16 lead package. The addressing, control and power connections for the 16K RAM use all of the 16 leads such that larger memories require more leads. In certain applications there is a demand for a 32K dynamic RAM in a single package and a technique for producing such a product is to combine two 16K RAMS into a single package. This approach, however, has a number of drawbacks. Although certain of the signals transmitted to and received from the corresponding leads in the two memories are such that the corresponding leads can be connected together, certain of the leads must be connected independently to the control circuit for the memory so that each of the memories can be operated independently. Thus, it is not possible to use a single memory circuit design and simply connect all of the leads in common.
There are also applications which call for the combining of larger memories to produce units having memory sizes of 64K, 128K and larger. Further, there are applications for combining multiple integrated circuits such as microprocessors and memories in a single unit.
One existing approach for providing a double density memory as described above is the fabrication of nonstandard memory circuits in which the circuits are designed specifically to have the majority of the physically corresponding leads connected in common and certain of the remaining leads connected to dedicated leads of the overall package. This technique permits the combining of two 16K random access memories each having a 16 lead package into a larger package having 18 leads. A primary drawback to this approach is the added expense required in fabricating parts dedicated for one specific application. If such parts do not meet the specific test requirements for the customer requiring the double density memory then the parts are typically not usable for conventional applications.
In view of these problems there exists a need for a package for housing a plurality of integrated circuits which are not uniquely fabricated for use in a combined configuration. Such a package can permit the grading of mass produced parts to select the desired grades for inclusion within the combined housing while using the other grades in conventional applications thereby eliminating the need for a unique circuit design and increasing the utilization of the circuits produced.


DISCLOSURE OF THE INVENTION

The present invention is a socket for containing at least two integrated circuits wherein the circuits are connected to operate independently through a plurality of package leads. Each of the integrated circuits is previously manufactured and encapsulated with a standard lead configuration. The socket includes a housing which has a planar member separating the interior of the housing into first and second square or rectangular chambers. A plurality of separator members are positioned adjacent opposed interior walls of the first and second chambers to form a plurality of recesses on the opposed walls of the chambers. A plurality of first metallic strips are included wherein each first metallic strip extends from within a recess in the first chamber through the plane of the planar member to within a corresponding recess in the second chamber and each first metallic strip is connected to a respective one of the package leads. The housing further includes a plurality of second metallic strips each one extending from within one of the recesses to connect to one of the package leads and the second metallic strips are located in corresponding recesses of the first and second chambers. Each of the first and second chambers is adapted to contain one of the integrated circuits wherein the leads of the integrated circuits are r

REFERENCES:
patent: 3555364 (1971-01-01), Matcovich
patent: 3753211 (1973-08-01), Pauza et al.
patent: 3757284 (1972-04-01), Klehm, Jr.
patent: 4079511 (1978-03-01), Grabbe
patent: 4080026 (1978-03-01), Gianni
patent: 4192565 (1980-03-01), Gianni
patent: 4224637 (1980-09-01), Hargis

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