Snooping of I/O bus and invalidation of processor cache for memo

Details Snooping of I/O bus and invalidation of processor cache for memo Snooping of I/O bus and invalidation of processor cache for memo

1994-10-21

1997-09-30

Gossage, Glenn

Boots, shoes, and leggings

395471, 395842, 395287, 395308, 364DIG1, 36424341, 364590, 3642423, 3649642, 3649644, 364DIG2, G06F 1300, G06F 1336, G06F 1340

Patent

active

056734140

ABSTRACT:
In a computer system that contains an input output (I/O) bus connecting to I/O devices, a central processing unit (CPU), a CPU cache memory, a system memory not directly accessible via the I/O bus, and a system bus used for conducting data transfers between the I/O bus and both the CPU cache and system memory, a method and apparatus are provided to allow addressable memory locations in both the system memory and I/O devices coupled to the I/O bus to be cacheable in the CPU cache. The I/O bus supports data transfers between pairs of I/O devices, as well as data transfers between individual I/O devices and the system which presents a problem of maintaining coherency in the CPU cache when data is written by one I/O device to a cacheable memory location in another I/O device. The present solution employs a snoop/data invalidation function at the system interface to the I/O bus to determine when a memory location in an I/O device coupled to the I/O bus is being written to by another I/O device coupled to the I/O bus. If such a write is taking place, it is then determined if the address of the location being written is in an address range predesignated as cacheable; if so, then the CPU cache controller or other device controlling the CPU cache is notified that memory at a cacheable location in an I/O device has been overwritten.

REFERENCES:
patent: 5119485 (1992-06-01), Ledbetter, Jr. et al.
patent: 5226144 (1993-07-01), Moriwaki et al.
patent: 5251310 (1993-10-01), Smelser et al.
patent: 5317720 (1994-05-01), Stamm et al.

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