Smooth clock switching for power managed PCI adapters

Details Smooth clock switching for power managed PCI adapters Smooth clock switching for power managed PCI adapters

1998-12-23

2001-09-18

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S144000, C327S099000

Reexamination Certificate

active

06292038

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor devices and more specifically to smooth clock switching between asynchronous clocks.
2. Background Information
Clock switching has become a concern in various ways in the semiconductor industry due to the necessity of having many different clocks within a system to run (or time) the various devices within the system. For example, many computers today include devices that are run at high power voltages and devices that are run at low power voltages all in the same system. Devices that run at higher voltages may require faster clocks while devices that run at lower voltages may require slower clocks. Thus, the passing of information or data from one device to another may require clock transitions from faster clocks to slower clocks and vice versa all within the same system.
Another example is with the advent of portable computers (or laptop computers). With laptop computers there is a need for power conservation to extend battery life. In other words, when the laptop is not in use the power consumption is decreased by going into a sleep mode, thus saving the battery life. When the laptop enters power conservation (or sleep) mode the laptop switches from a relatively faster clock to a slower clock. When the laptop leaves the sleep mode to enter normal operation the laptop then switches from the slower clock to the faster clock.
Yet another consideration in computer systems is the idea of networking many computers together to run on the same system network. For example, when powering down a computer on a network the computer may look like it is “off” but really it has been powered down while the network is still running. This powering down of the computer requires the computer to switch from a relatively faster clock to a slower clock so that the computer appears to be off while the network remains running in the background. When the computer is then later powered up, the computer must switch from the slower clock back to the faster clock in order to run at a sufficient speed for the user.
Switching between different clocks and clock cycles becomes particularly problematic when the clocks are not synchronous to one another (i.e. asynchronous clocks). Switching between two asynchronous clocks may cause a “glitch” to occur and the device may enter a metastable state which in turn may cause system problems. For example, when switching from a relatively faster clock to a slower clock if the transition is performed at the time when the faster clock is on an upswing (i.e. transitioning high) and the slower clock is on a downswing (i.e. transitioning low) then the pulse (the transition from high to low) may be too fast to enter the system causing a glitch. It should be noted that glitches may occur under other circumstances and that the above example was given merely to be illustrative.
FIG. 1
illustrates an example of when (or how) a glitch may occur. In
FIG. 1
there are two clocks running at the same time however the primary clock CLK A
110
is running relatively faster than the alternate CLK B
120
. At the outset the system is running using CLK A
110
. At some point, however, it becomes desirous to switch clocks to CLK B
120
. Up until the switch is made Select A is high (SEL A
115
) and Select B is low (SEL B
125
), but at the switch SEL A
115
is driven low
116
and SEL B
125
is driven high
126
. As illustrated in the resultant clock
150
, the system runs using CLK A
110
and then after the switch the system runs using CLK B
120
. Because the down swing
116
of CLK A
110
and the upswing
126
of CLK B
120
are so close in “time” the resultant clock exhibits a narrow pulse or “glitch”
180
. Such a narrow pulse may be too fast to enter the system.
In the example of the networked computers a glitch may throw the microengine in an ethernet controller off causing the system to miss an instruction or skip an instruction. Therefore, switching between two asynchronous clocks cannot be blindly performed.
Thus, what is needed is a method and apparatus for switching between asynchronous clocks and performing this switch in a smooth transition without glitches.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for switching between a first clock and a second clock wherein the first and second clocks are asynchronous to one another without exhibiting the problem of glitches.
Additional features and benefits of the present invention will become apparent from the detailed description, figures, and claims set forth below.


REFERENCES:
patent: 4821229 (1989-04-01), Jauregui
patent: 4970405 (1990-11-01), Hagiwara
patent: 5099141 (1992-03-01), Utsunomiya
patent: 5768602 (1998-06-01), Dhuey
patent: JP401044114A (1989-02-01), None

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