Smart lock-in circuit for phase-locked loops

Details Smart lock-in circuit for phase-locked loops Smart lock-in circuit for phase-locked loops

2007-05-29

2007-05-29

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S017000, C331SDIG002

Reexamination Certificate

active

11036837

ABSTRACT:
The smart lock-in circuits basically include a sensor, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensor, the output voltage of the sensor turns on the corresponding transistor, which provides a current to its output until the voltage at feedback reaches the midpoint voltage. The time to reach the midpoint voltage at a filter is simply equal to the charge stored at the filter divided by the current, which can be scaled by a device aspect ratio of the transistor. Consequently, all smart lock-in circuits provide an initial loop condition closer to the expected loop condition according to schedule.

REFERENCES:
patent: 6229403 (2001-05-01), Sekimoto
patent: 2003/0214361 (2003-11-01), Nishikido
patent: 2005/0088247 (2005-04-01), Yasui

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