Small-sized digital generator producing clock signals

Details Small-sized digital generator producing clock signals Small-sized digital generator producing clock signals

2001-10-30

2003-12-23

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S261000, C331S057000

Reexamination Certificate

active

06667646

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to phase-locked loop type clock-signal generators that produce a high-frequency clock signal from a low-frequency clock signal. Among these generators, the invention relates more specifically to those using a digital oscillator producing clock signals whose period is proportional to a binary number received by the oscillator.
BACKGROUND OF THE INVENTION
A prior art generator
10
according to
FIG. 1
has a comparator
12
, a binary number decoder
14
and a digital oscillator
20
that are series connected. An output of the oscillator
20
is connected to an input of the comparator
12
. The generator
10
provides a high-frequency signal CKHF (with a period PHF) from a low-frequency reference signal CKBF (with a period PBF).
The comparator
12
has two inputs to which the high-frequency signal CKHF and the reference signal CKBF are applied. The comparator
12
compares the period PHF of the clock signal CKHF with a desired period PHF
0
. The desired period PHF
0
is, for example, a multiple of the period PBF. At N serial outputs, the comparator
12
produces a number NR in the form of N=2
N
binary signals S(
1
), . . . , S(N) representing the bits of NR. The number NR has the following characteristics: NR increases if PHF<PHF
0
, NR decreases if PHF>PHF
0
, otherwise NR is constant.
The binary signal decoder
14
has N inputs connected to the outputs of the comparator
12
. The decoder
14
provides decoded binary clock signals SD(
1
), SD(
2
), . . . , SD(2
N
) at 2
N
serial outputs. These decoded binary signals indicate the value of the number NR given by the counting circuit: S(NR+1)=1, and S(i)=0 for all values of i ranging from 1 to 2
N
, and i≠NR+1.
The digital oscillator
20
receives the binary signals SD(
1
), SD(N), . . . , SD (2
N
) and produces the clock signal CKHF at a serial output OUT. The oscillator
20
is shown in FIG.
2
. It comprises 2
N
−1 elementary cells A(
1
) to A(2
N
−1) that are identical, and one cell B that is different from the cells A(j), with j being an integer ranging from 1 to 2
N
−1. Each cell A(j), B comprises a data input e and a data output s.
The input e of the cell B is connected, first, to its output s by a switch INT(
1
) controlled by the signal SD(
1
) and, second, to the output of the cell A(
1
). The input of each cell A(
1
) to A(2
N
−2) is connected, first, to the output s of the cell B by a switch INT(
2
) to INT(2
N
−1) controlled by the signal SD(
2
) to SD(2
N
−1) and, second, to the output of the next cell A(
2
) to A(2
N
−1). The input of the cell B is connected to the output of the cell A(
1
), and the output of the cell A(2
N
−1) is connected to the output of the cell B by a switch INT(2
N
) controlled by the signal SD(2
N
). The switch INT(i), with i ranging from 1 to 2
N
, is closed when the signal SD(i) is active. If not it is open.
The output of the cell B is the output OUT of the oscillator
20
at which the high-frequency CKHF is given. The cell B comprises an odd number NB of series connected primary inverters, with NB≧1. The output of the first inverter is connected to the output of the cell B, and the input of the NB
th
inverter is connected to the input e of the cell B. The cell B is equivalent to an inverter whose propagation times (downward propagation time TB
0
and upward propagation time TB
1
≠TB
0
) are greater than the propagation times of the primary inverters that form it.
Since all the cells A(
1
) to A(2
N
−1) are identical, only the first cell A(i=1) is described in detail in FIG.
2
. The first cell comprises an even number NA of identical primary inverters (in the example of
FIG. 2
, NA=2) series connected with a switch INTA(i=1) controlled by the signal SD(i=1) by an inverter. The input of the last inverter is connected to the input of the cell A(
1
), and the output of the switch INTA(
1
) is connected to the output of the cell A(
1
). The switch INTA(
1
) is open when SD(
1
) is active. If not it is closed.
The switch INTA(
1
) is necessary for isolating the primary inverters from one another. Without the presence of the switch INTA(
1
), the output of an inverter of the cell A(
1
) and the output of an inverter of the cell B would be short-circuited at the closing of the switch INT(
1
).
A cell A(
1
) to A(2
N
−1) comprises a number NA of inverters. It is equivalent to a delay circuit. The cell transmits the signal that it receives at its input to its output, after a period of time TA
0
if the signal is equal to 0, or after a period of time TA
1
if the signal is equal to 1. The propagation times TA
0
, TA
1
are different from each other because the propagation time of a 0 in a switch INTA is different from the propagation time of a 1 in the same switch.
The clock signal generator
10
works as follows. The comparator
12
provides a number NR ranging from 0 to 2
N
−1 and produces an associated signal SD(NR+1)=1, with the other signals SD(i≠NR+1) being all zero signals. The switch INT(NR+1) controlled by the signal SD(NR+1) closes and the switch INTA(NR+1) opens. NR cells A are selected to form, with the cell B, a looped chain of cells A, B in the oscillator
20
.
The propagation time of a 0 between the input and the output of the chain of cells is equal to T
10
=NR*TA
0
+TB
1
, and the propagation time of a 1 between the input and output of the chain of cells is equal to T
11
=NR*TA
1
+TB
0
. The period PHF of the high-frequency signal CKBF obtained at the output OUT of the oscillator is equal to PHF=T
10
+T
11
=NR*(TA
1
+TA
0
)+(TB
1
+TB
0
). It is therefore proportional to NR.
If the period obtained PHF is smaller than the desired period PHF
0
, then the number NR is increased by the comparator
12
to increase the number of cells A in the chain of cells, and thus increase the period PHF of the signal CKHF. Conversely, if the signal obtained PHF is greater than the desired period PHFO, then the number NR is diminished by the comparator
12
to diminish the number of cells A in the loop, and thus reduce the period of CKHF.
In other words, in the oscillator
20
, the total number of cells, and therefore the total number of inverters in the chain of cells, varies as a function of the number NR given by the comparator
12
, and the period PHF of the clock signal obtained is proportional to NR. The total number of inverters in the chain, however, must be an odd number in order that there may be oscillations.
Furthermore, when NR increases (or decreases) by one, a cell A is added (or eliminated) in the chain. It may be recalled that a cell A comprises an even number NA of inverters and a switch INTA.
The minimum variation of the period of a signal CKHF produced by the oscillator
20
defines the uncertainty on the period of the signal CKHF, in other words, the precision of the oscillator. For the oscillator
20
, the uncertainty on the period is therefore equal to TA
0
+TA
1
, with TA
0
and TA
1
being the propagation time of a 0 and a 1 in a cell A comprising an even number of inverters and a switch INTA.
By way of an indication, exemplary embodiments of switches INT(
1
), . . . , INT(2
N
) and primary inverters used in the cells A(
1
), . . . , A(2
N
−1), B are shown in
FIGS. 3
a
and
3
b
. When a switch has to be series connected with an inverter, as is the case in the cells A(
1
), . . . , A(2
N
−1), then these two elements are preferably made in the form of a single circuit like that of
FIG. 3
c
, which shows an inverter switch.
A first problem of signal generators such as that of
FIG. 1
is the large size of these circuits. The decoders include a set of at least 2
N
logic gates, with at least one per binary signal SD(i) being produced. The decoders thus become bulky very soon when the number n rises.
A second problem of existing generators is related to the construction of inverter-bas

Affiliated with

Also associated with

Rating

Small-sized digital generator producing clock signals does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Small-sized digital generator producing clock signals, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Small-sized digital generator producing clock signals will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3119340