Small size, low consumption, multilevel nonvolatile memory

Details Small size, low consumption, multilevel nonvolatile memory Small size, low consumption, multilevel nonvolatile memory

2001-10-04

2003-04-01

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Floating gate

Multiple values

C365S185180, C365S185210, C365S207000

Reexamination Certificate

active

06542404

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a small size, low consumption, multilevel nonvolatile memory.
2. Description of the Related Art
As is known, multilevel nonvolatile memory cells are normally read through analog sense amplifiers which supply at output analog voltages that are substantially proportional to the threshold voltages of respective cells selected for reading. These output voltages are then converted into corresponding digital signals through analog-to-digital converters.
In order to reduce errors in the reading phase, the sense amplifiers and the analog-to-digital converters are normally supplied with boosted supply voltages, higher than the external supply voltage generated by special voltage boosting circuits (for example charge pumps). In this way, in fact, one can avoid compressing the dynamic of the signals detected (cell voltages) with voltage translators to adapt it to the input dynamic of converters supplied with the external supply voltage; consequently, the voltage levels corresponding to the data stored in the memory cells are well separated from each other and the probability of error is low.
In particular, the analog-to-digital converters comprise at least one comparator, for example of the type described in “Design Techniques for High Speed, High Resolution Comparators,” by B. Razavi, B. Wooley, IEEE Journal Solid State Circuits, Vol. 27, No. 2, 1992.
This comparator is illustrated in FIG.
1
and is indicated with the reference number
1
. The comparator I has a pair of input terminals
1
a
,
1
b
connected to outputs of a sense amplifier not shown and a first and a second output terminal
1
c
,
1
d
and comprises an amplification stage
2
and a latch stage
3
. The amplification stage
2
is formed by a fully differential transconductance operational amplifier and has an inverting input and a non inverting input connected, on one side, to the input terminals
1
a
and
1
b
, respectively, of the comparator
1
through respective input switches
5
controlled in phase with each other, and, on the other side, to ground through respective first equalization switches
6
controlled in phase with each other and in phase opposition with respect to the input switches
5
.
The latch stage
3
comprises a latch amplifier
8
and a pair of feedback branches
10
.
The latch amplifier
8
, which is fully differential, has an inverting input
8
a
and a non inverting input
8
b
, and an inverting output and a non inverting output, connected respectively to the non inverting output and to the inverting output of the amplification stage
2
.
The feedback branches
10
each comprise a non inverting driving stage
11
and a sampling capacitor
12
, connected to each other in series, and are respectively placed between the inverting output and the inverting input
8
a
and between the non inverting output and the non inverting input
8
b
of the latch amplifier
8
, to define positive feedback loops. Output terminals of the driving stages
11
define the first and the second output terminal
1
c
,
1
d
of the comparator
1
.
The latch stage
3
further comprises a pair of second equalization switches
14
, connected between a respective input
8
a
,
8
b
of the latch amplifier
8
and ground; a pair of latch switches
13
, each connected between a respective input
8
a
,
8
b
of the latch amplifier
8
and a respective sampling capacitor
12
; a pair of sampling switches
15
, each connected between a respective sampling capacitor
12
and ground. The second equalization switches
14
are controlled in phase with each other and in phase opposition with respect to the latch switches
13
; the sampling switches
15
are opened simultaneously and closed in advance with respect to the second equalization switches
14
.
The comparator
1
further comprises a single supply line
18
to which are connected respective supply terminals of the amplification stage
2
, of the latch amplifier
8
and of the driving stages
11
.
Since the amplification stage
2
must have a wider input dynamic than that allowed by the supply voltages normally available in nonvolatile memories, on the supply line
18
there must necessarily be a boosted voltage V
p
, higher than the supply voltage.
So, in the known comparators, also the latch amplifier
8
and the driving stages
11
receive the same boosted voltage V
p
supplied to the amplifying stage
2
and all the currents absorbed by the comparator
1
during operation must be supplied through the supply line
18
.
This is a considerable drawback since, as already mentioned, the boosted voltage V
p
must be generated by special charge pump circuits (not shown here) which can supply currents with a not excessively high value, as is known. Consequently, several charge pumps must be realized, working in parallel, so that the respective currents can be combined in order to provide the total current required by the comparators
1
present in the analog-to-digital converters of the nonvolatile memory. However, the realization of the charge pumps involves the occupation of a considerably large area, which is a particular disadvantage. Moreover, the use of the boosted voltage V
p
for all the components of the comparator
1
determines a high power absorption.
BRIEF SUMMARY OF THE INVENTION
An embodiment of the present invention realizes a multilevel nonvolatile memory that is free from the drawbacks described.
The multilevel nonvolatile memory includes a supply line at a supply voltage; a boosting circuit having an input connected to the supply line and an output supplying a boosted voltage higher than the supply voltage; a boosted line connected to the output of the boosting circuit; and a reading circuit. The reading circuit includes a comparator having a first and a second input, a first and a second output, an amplification stage, and a latch stage. The amplification stage has a supply terminal connected to said boosted line and the latch stage presents a supply terminal connected to the supply line.


REFERENCES:
patent: 5995412 (1999-11-01), Ohta
A. Pierin et al., “High-Speed Low-Power Sense Comparator for Multilevel Flash Memories”, Proc. IEEE International Conference on Electronics Circuits and Systems(ICECS), Jourieh(Lebanon), Dec. 2000, pp 759-763.
B. Razavi et al., “Design Techniques for High-Speed, High-Resolution Comparators”, Dec. 12, 1992, vol. 27, No. 12, pp. 1916-1926.

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