Small emitter and base-collector bi-polar transistor

Details Small emitter and base-collector bi-polar transistor Small emitter and base-collector bi-polar transistor

2001-06-15

2004-02-24

Thomas, Tom (Department: 2811)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

C438S343000

Reexamination Certificate

active

06696342

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to high speed bi-polar junction transistors.
BACKGROUND OF THE INVENTION
As RF technology continues to develop, in particular in the fields of optical networking and wireless transmissions, higher frequencies are constantly being sought. As a result, transistor sizes have to be reduced in order to decrease junction compacitance and reduce the current and heat dissipation. Attempts have been made at reducing the base-emitter junction area to reduce the capacitor effect of the junction. However, these devices still display large base-collector junction areas resulting in a high capacitance at the base collector junction, which will therefore set the upper limit on the speed that the device can handle.
In the prior art device, illustrated in
FIG. 1
, dielectric spacers in the form of oxide and nitride posts, are used inside a base polysilicon window thereby achieving a self-aligned bi-polar junction transistor (BJT) with an emitter region smaller than photolithography limits. The device of
FIG. 1
is formed with a base polysilicon layer
10
. Using a mask etching step, a window is etched through to the base polysilicon
10
. Thereafter, the posts are formed on either side, each comprising an-oxide post
14
sandwiched between two nitride posts
16
. A second polysilicon layer
18
is then deposited to define the emitter
20
. As can be seen from
FIG. 1
, the junction between the emitter poly
20
and the base poly
10
is reduced due to the reduced emitter size caused by the dielectric spaces
12
,
14
,
16
. However, the base area
22
remains relatively large since it includes not only the two base contacts, but also the two sets of spaces, and the width of the emitter, each being about 0.1 &mgr;n. From each of these dimensions, the total base width, which defines the base-collector junction area, is approximately 0.5 &mgr;m thereby giving a basecollector area that is approximately five times greater than the base-emitter junction area. Ideally, the two junction areas should be approximately of the same order of magnitude.
The second prior art device is illustrated in
FIG. 2
which uses a polysilicon spacer
30
as a diffusion source to form a very small emitter region
32
. However, in order to form the base contact
34
, boron is implanted into the base
36
. In order to avoid the boron doping the polysilicon, a separate mask is required to shield the polysilicon. This need for a second mask thus forfeits the benefits of a self-aligned mask. Furthermore in order to ensure that the boron does not inadvertently impinge upon the polysilicon, the mask has to extend sufficiently far across the base to take account of alignment difficulties. This results in a large emitter to extrinsic base separation, and therefore a large base-collector junction area. This embodiment has the additional problem of not stopping sacrificial polysilicon etching at the base epi surface which can lead to increased leakage due to damage of the silicon crystal lattice.
Thus a need exists for a BJT structure with sub-lithography dimensions that does not suffer from the drawbacks of the prior art.
SUMMARY OF THE INVENTION
According to the invention, there is provided a method of reducing the base-emitter junction area and the base-collector junction area in a bi-polar junction transistor (BJT), comprising using a single poly layer as a contact to both the base and the emitter regions of the BJT.
Preferably the method includes etching a nitride/oxide stack using the poly as a mask, to define a window for a base. The etching preferably involves an oxide etch process and typically includes overetching the oxide and then growing the base. The method typically also includes etching away the nitride between the grown base and the poly layer using a wet etch process, to define a gap region for the emitter. Typically, the emitter is formed by an epi process to fill the gap region, followed by an a doping of the epi in the gap region. The doping may be achieved by diffusing a dopant into the epi from the poly using an annealing step.
Further, according to the invention there is provided a method of forming a small base and emitter in a BJT, comprising etching a region for a base and an emitter into an oxide, using a poly layer as a mask wherein an oxide etch process is used and the poly layer is protected by nitride layers during the oxide etch process, and wherein at least a portion of one of the nitride layers is removed using a nitride etch process to define a region for the emitter.
Still further, according to the invention, there is provided a method of forming a base and an emitter in a BJT, comprising using a first etch process to form a region for the base, and using a second etch process to define a region for the emitter. Typically the first etch process is used to over etch an oxide layer under a poly layer. The second etch process typically includes etching away at least part of a nitride layer between the poly layer and the oxide layer.


REFERENCES:
patent: 5406113 (1995-04-01), Horie
patent: 5420454 (1995-05-01), Vook et al.
patent: 6043552 (2000-03-01), Miwa
patent: 6271577 (2001-08-01), Havemann
patent: 6368946 (2002-04-01), Dekker et al.
patent: 6380017 (2002-04-01), Darwish et al.
patent: 6521974 (2003-02-01), Oda et al.

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