Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
2001-07-16
2004-08-10
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S275000, C257S276000, C257S288000, C257S522000, C257S523000
Reexamination Certificate
active
06774416
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to transistors capable of operating at mm-wave frequencies, and specifically to microwave/mm-wave cascode transistor structures.
2. Description of Related Art
Cascode circuits have been in use in the electronics industry for decades, first using vacuum tubes, and later, field effect transistors. Cascode transistor circuit elements are the basic building blocks of many hybrid and integrated circuits. Much of the early cascode circuit work was focused on low frequency applications. Therefore, cascode FET layouts for small area transistor monolithic microwave integrated circuits (MMIC) and mm-wave frequency operations were not developed early on. Today, high volume commercial radio markets at mm-wave frequencies (30 GHz and higher) are driving the need for new, small area MMIC amplifiers and circuits, which require a different transistor design and layout approach to achieve MMIC area and cost goals.
A simple circuit schematic of two FETs
100
A and
100
B in a cascode configuration
170
is shown in FIG.
1
. The RF input is to the gate
130
A of the common source FET
100
A at the left, and the RF output is to the drain
120
B of the common gate FET
100
B at the right. The drain
120
A of the common source FET
100
A interconnects with the source
150
B of the common gate FET
100
B. The source
150
A of the common source FET
100
A is connected to ground
180
. In most circuit applications, the gate
130
B of the common gate FET
100
B is RF grounded, using capacitors to ground
180
. This is typically achieved using metal-insulator-metal (MIM) capacitors
300
on GaAs MMICs, and via grounds, to “ground” the bottom plate of the capacitor to the backside of the MMIC.
The common source
100
A and common gate
100
B FETs typically have the same gate
130
A and
130
B widths in a cascode structure
170
, but this is not an absolute requirement. The gate
130
A and
130
B widths can be different, and if so, this requires a more complex biasing scheme for such a structure, because one FET has a higher IDSS (saturated drain-source current) than the other.
FIG. 2
shows two interdigitated FETs
100
A and
100
B in a conventional cascode configuration
170
and layout, i.e., a cascade of a common source FET
100
A with a common-gate FET
100
B. Each FET
100
includes a plurality of transversely spaced Metal-Schottky field effect transistor (MESFET) unit cells fabricated on a GaAs substrate, each including a doped source, drain and channel regions (not shown) formed within an active region
110
of the GaAs substrate. Each FET
100
further includes a plurality of parallel, elongated drain fingers
125
which overlie the drain regions of the MESFETs, and which are in electrical connection therewith. The drain fingers
125
of both FETs
100
are interconnected together at one end by a drain manifold
120
. Each FET
100
further includes a plurality of source fingers
150
in electrical connection with the source regions of the MESFETs interspersed between the respective drain fingers
125
. Furthermore, a plurality of gate fingers
135
in electrical connection with the channel regions of the MESFETs are interspersed between the respective drain fingers
125
and source fingers
150
. The gate fingers
135
are interconnected together at one end by respective gate manifolds
130
.
The drain manifold
120
A of the CS FET
100
A provides the input to the source fingers
150
B of the CG FET
100
B via drain air bridges
160
overlying the gate manifold
130
B of the CG FET
100
B. The drain manifold
120
B of the CG FET
100
B enables the drain fingers
125
B of the CG FET
100
B to be collectively connected to external circuitry. The gate manifold
130
A of the CS FET
100
A provides the input signal to the gate fingers
135
A of the CS FET
100
A in parallel, whereas the gate manifold
130
B of the CG FET
100
B is connected by metal-insulator-metal (MIM) capacitors (not shown) to a ground plane (not shown) on the opposite side of the GaAs substrate. This provides RF ground to the gate
130
B of the CG FET
100
B.
Source connection pads
140
provided on either side of the CS FET
100
A are connected to the ground plane on the opposite side of the GaAs substrate by electrically conductive vertical interconnects or vias
145
. The source fingers
150
A of the CS FET
100
A are connected to the source connection pads
140
by electrically conductive source air bridges
155
. The source air bridges
155
extend over the drain fingers
125
A and gate fingers
135
A and are connected to the metallization of the source fingers
150
A. However, the large source via grounds
145
in the source connection pads
140
of the conventional cascode FET structure
170
of
FIG. 2
take up significant MMIC area.
SUMMARY OF THE INVENTION
A small area cascode FET structure capable of operating at mm-wave frequencies cascades a common source (CS) FET with a common gate (CG) FET, in a smaller physical area than conventional cascode FET structures. The small area of the exemplary cascode FET structure is partially achieved by using small source via grounds, requiring a thin gallium arsenide (GaAs) substrate (typically between 50 and 70 microns thick). The overall cascode area is reduced further, by having the two FETs share a common node. This common node is the output drain manifold of the CS FET, which is also an input source finger of the CG FET. In addition, small via grounds within the MIM capacitors further reduce circuit area. These features make the overall cascode FET structure much smaller in area than one could achieve using two separate common source and common gate reduced size FETs. Advantageously, the small area cascode FET can be applied to many different MMICs to reduce MMIC area requirements and cost.
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PCT Notification of Transmittal of the International Search Report dated Aug. 27, 2003.
Jenkens & Gilchrist PC
Nanowave, Inc
Ortiz Edgardo
Wilson Allan R.
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