Slurry composition and method of chemical mechanical...

Abrasive tool making process – material – or composition – With inorganic material

Reexamination Certificate

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C051S309000, C106S003000, C438S692000, C438S693000, C510S397000, C423S593100, C423S595000, C423S594120, C423S598000, C423S599000, C423S600000

Reexamination Certificate

active

06251150

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to slurry compositions for polishing substrates and more particularly to slurry compositions that include spinel particles for the chemical mechanical polishing of substrates.
BACKGROUND OF THE INVENTION
Chemical mechanical polishing or planarization (CMP) is a rapidly growing segment of the semiconductor industry. CMP provides global planarization of the wafer surface thus improving the coverage of the wafer with dielectric (insulators) and metal substrates. This planarity also increases lithography, etching and deposition process latitudes.
CMP has been evolving for the last fifteen years and has been adapted for the planarization of inter-layer dielectrics (ILD) for multi-layered metal (MLM) structures. In particular, CMP has been successfully applied to the planarization of interdielectric levels of silicon oxides, BPSG, silicon nitride and also metal films. Some of the surfaces of current interest include tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), silicon nitride (SiN), low-K and high K dielectric, silicon, polysilicon, tetraethoxysilane (TEOS), tantalum nitride (Tan) and boron phosphorous silicate glass (BPSG) surfaces.
In the semiconductor industry, the role of CMP is becoming increasingly important as computer chips are being modified for increased performance. In particular, feature sizes of computer chips continue to be reduced, the number of metal layers or “wires” and the length of “wires” per chip continue to be increased, and the operating frequency of chips also continue to be increased. It is expected that in 2001, DRAM chips will have a memory of 1 gigabit and a typical CPU will have 13 million transistors/cm
2
. These performance improvements in computer chips increase the need for a three dimensional construction on the wafer chip to reduce delays of the electrical signals and for methods to produce these constructions. Therefore, as these changes become implemented, and especially as features sizes become smaller, the planarity requirements for better lithography will become critical.
To meet these new demands, certain aspects of conventional CMP methods must also be improved. For example, there is an increased emphasis on reducing CMP defects in metal and insulator layers, producing better planarity within the wafer and between wafers, avoiding pre-mixed concentrates that require point-of-use mixing, providing a high polishing selectivity, improving post-CMP cleaning methods, and providing better end-point detection (EPD). There are also environmental, health and safety issues associated with CMP and post-CMP cleaning such as reducing the requirement for vapor handling, providing slurry recycling or more environmentally friendly slurry residues, and producing more stable chemistries for use with abrasives.
The conventional CMP process used for polishing wafers typically consists of the rotation of a wafer on a rotary platen in the presence of a polishing medium and a polishing pad that grinds away the surface material. The CMP process is actually considered to be a two-part mechanism: the chemical modification of the surface of the material and the mechanical removal of the modified material by mechanical grinding. The challenge of the process is to control the chemical action on the substrate and the rate of the grinding while maintaining a high selectivity or preference for removing the offending wafer features without significant damage to the desired features.
An additional concern is that CMP processes are very sensitive to structural pattern density. In particular, large area features are planarized slower than small area features. As a result, polishing wafers having features with varying areas can result in metal structure “dishing” wherein metal plug connectors are recessed below the planarized surface. Furthermore, oxide erosion can also occur, which results in removal of desired oxide features. Both “dishing” and oxide erosion negatively affect the operation of the wafer.
Furthermore, there are different issues associated with polishing different types of surfaces. For example, CMP slurries for metal polishing must have a high metal removal rate (1000's Å/min) and must also have high selectivity so that they remove metal and not the dielectric features on the wafers. This type of polishing relies on the oxidation of the metal surface and the subsequent abrasion of the oxide surface with the CMP slurry composition. The general oxidation reactions are as follows (M=metal atom):
M
o
→M
n+
+ne

M
n+
+[Ox]
y
→MO
x
or [M(OH)
x
]
Under ideal conditions, the rate of metal oxide (MO
x
) formation V
F
will equal the rate of metal oxide polishing V
p
, that is V
F
=V
p
. The removal rate for the metal surface is typically between 1700 and 7000 Å/min. In addition, the polishing selectivity of metal to dielectric generally ranges from 20:1 to 100:1, depending on the metal type, and can be even as low as 1:1.
The pH of slurry used for polishing can greatly affect the polishing process. If the pH is too low then the chemical agents in the slurry can rapidly penetrate the metal oxide and attack the metal, such that V
F
<V
p
, thus exposing the metal without any further oxide formation. When this occurs, the metal surfaces, both at high points and in valleys, are removed at the same rate. Thus, planarization of the surface is not achieved. In addition, this situation can cause “dishing” as described above, which eventually leads to poor step coverage and possibly poor contact resistance. Alternatively, if the pH is too high, the oxide layer formed on the surface of the metal can become essentially impenetrable to the chemical agents in the slurry. In this case, the metal becomes passive, such that V
F
>V
p
and the metal polishing rate becomes slow.
One particular problem with some metal slurries is that the low pH and highly corrosive oxidants being used with in the metal CMP process can corrode polishing equipment. For example, slurries that include ferric nitrate oxidizing agents require a low pH and these slurries are known to stain and corrode polishing equipment.
In addition, because of chemical stability problems, many slurries must be prepared at the point of use because they have little or no pot life. For example, slurries that include hydrogen peroxide oxidizing agents are generally not stable when premixed with the other slurry components and therefore have to be delivered to the polishing equipment with separate pumping systems and mixed at the point of use. Moreover, other slurries, such as those that use potassium iodate system require special handling. Metal polishing slurries can also contribute to mobile ion contamination, can affect the slurry particle distribution and compositions, and can be toxic to the environment.
There are similar problems and concerns associated with the polishing of ILD (oxide) surfaces. One particular concern with ILD polishing is surface damage such as scratching. Other important concerns in ILD polishing include polishing rate, planarity, and wafer polishing uniformity both within the wafer and from wafer to wafer.
The CMP mechanisms of ILD polishing are still being developed, but the polishing process appears to involve two concurrent processes: a mechanical process involving plastic deformation of the surface; and chemical attack by hydroxide (

OH) to form silanol bonds. The chemical reactions are believed to occur as follows:
As with metal polishing slurries, the pH for ILD polishing slurries is important. Specifically, for silicon oxide, the pH should to be between 10 and 11.5. If the pH is too high, the polynuclear species may start to precipitate in an unpredictable manner. This precipitation can lead to gelling, which can lead to microscratches. There is also the possibility that the oxidation process will form Si—O—Si bonds as shown in equation (4) above. The formation of Si—O—Si bonds basically occ

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