Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Generating sawtooth or triangular output
Reexamination Certificate
1999-12-02
2001-11-13
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Generating sawtooth or triangular output
C327S170000
Reexamination Certificate
active
06316972
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to slope generators for generating a slope between a first and a second voltage level.
BACKGROUND OF THE INVENTION
Slope generators (also referenced as waveform, ramp or sawtooth wave generators) are used in several applications for generating signals with a controllable slope. Typically, a current integrating capacitor is charged/discharged to produce a ramp signal.
FIG. 1
depicts a slope generator
10
as known in the art, e.g. a 1DB6 (“Snake”) Slope Generator IC as used in the Hewlett-Packard HP8112A. The slope generator
10
comprises a fixed connected current source
20
providing a charge current I_up to load a ramp-capacitor C_ramp from a voltage low level V_l to a voltage high level V_h as output voltage V_out at a node
25
. A current source
30
switchable by a current switch
40
(consisting of transistors Q
1
and Q
2
) provides a current I_dn (whereby I_dn>I_up) to discharge the ramp-capacitor C_ramp from voltages V_h to V_l with a discharge current of I_dn−I_up. An input pulse V_in with fast edges at the current switch
40
controls the coupling of the current source
30
to the ramp-capacitor C_ramp. A low-level of the input pulse V_in switches on I_dn and a high level of the input pulse V_in switches off I_dn.
With the current I_dn being turned off, the ramp-capacitor C_ramp will be charged with a constant current I_up (thus generating a rising slope with the slew rate of dV/dt=I_up/C_ramp) until a clamping diode D
2
(coupled to a clamping voltage V_cl_h) is taking over this current, thus stopping the charging. With I_dn being turned on, the ramp-capacitor C_ramp will be discharged with a constant current I_dn−I_up (thus generating a falling slope with the slew rate of dV/dt=−(I_dn−I_up)/C_ramp) until a clamping diode D
1
(coupled to a clamping voltage V_cl_l) is taking over this current, thus stopping the discharging.
The voltage levels V_l and V_h of the output voltage V_out at the ramp node
25
of the ramp-capacitor C_ramp are derived from the clamping voltages V_cl_l and V_cl_h:
V
—
l=V
—
cl
—
l
(
I
_dn−
I
_up,
T
)−
Vf
—
D
1
(I_dn−
I
_up,
T
) (1a)
V
—
h=V
—
cl
—
h
(
I
_up,
T
)+
Vf
—
D
2
(
I
_up,
T
) (1b).
The clamping voltage V_cl_l and the forward voltage Vf_D
1
at diode D
1
are both dependent on the differences between the currents I_dn and I_up and on the temperature T. Accordingly, the clamping voltage V_cl_h and the forward voltage Vf_D
2
at diode D
2
are both dependent on the current I_up and the temperature T.
The time to charge the capacitor C_ramp and thus the rising time T_rise of the slope generator
10
is:
T
—
rise
=
C
—
ramp
×
&LeftBracketingBar;
V
—
h
-
V
—
1
&RightBracketingBar;
I
—
up
.
(
2
)
Accordingly and with I_dn>I_up, the time to discharge the capacitor C_ramp and thus the falling time T_fall of the slope generator
10
is:
T
—
fall
=
C
—
ramp
×
&LeftBracketingBar;
V
—
h
-
V
—
1
&RightBracketingBar;
&LeftBracketingBar;
I
—
dn
-
I
—
up
&RightBracketingBar;
.
(
3
)
As apparent from equations (2) and (3), the timing of the slope generator
10
directly depends on the voltage levels V_h and V_l. Therefore, significant effort has to be spent to compensate the thermal and current dependency of the clamping diodes D
1
and D
2
.
Another, even more serious disadvantage of the slope generator
10
of
FIG. 1
is the capacitive loading by two clamping diodes (D
1
and D
2
), thus limiting the minimum feasible ramp-capacitance C_ramp_eff, and accordingly, the minimum feasible transition times T_rise and T_fall. This is since the fastest slope (or transition time) is determined by the highest possible charging current and the lowest possible capacitance at the node
25
, whereby the capacitance at the node
25
is determined by the capacitor C_ramp and parasitic capacitances. On the other hand, the parasitic capacitance of the clamping diodes D
1
and D
2
exhibits a strong dependency on the applied voltages, thus resulting in a negative impact on a desired linear slope. Since V_cl_l and V_cl_h represent low impedance nodes, the influence of parasitic capacitance of the clamping diodes D
1
and D
2
will add fully to the ramp capacitor C_ramp.
SUMMARY OF THE INVENTION
It is an object of the invention to provide an improved slope generator with a more accurate level clamping.
The object is solved by independent claim
1
. Preferred embodiments are shown by the dependent claims.
A slope generator according to invention generates, in response to an input signal, a slope between a first and a second voltage level of an output voltage at an output node. The slope generator comprises a capacitor coupled to the output node, a first current source for providing a first current to the output node, and a second current source for providing a second current to the output node controlled by a first current switch. A control electrode of a first current path of the first current switch is coupled to and controlled by an input signal and a second current path is coupled to the output node. The first current switch provides the first and the second voltage levels, or corresponding voltage levels derived therefrom, to the output node.
According to the invention, the first current switch represents a combined current switching/voltage level providing (clamping) circuit, thus diminishing the influence of parasitic capacitance loads at the ramp-node.
In a preferred embodiment, the first current switch comprises two emitter-coupled transistors and a control electrode of the second current path is coupled to the output node. In contrast to the prior art as depicted in
FIG. 1
, wherein two diodes are connected to a low impedance node, this inventive embodiment provides just one diode connected to a low impedance node, thus allowing faster transition times for given ramp capacitor, charge currents and ramp voltage swings. Thus, the ‘clamping principle’ is to go—from the voltage levels V_l and V_h—one diode drop down and then one diode drop up again, thus directly transferring V_h and V_l to the ramp node. With matching diodes, all temperature and current dependencies are cancelled out with a very simple circuitry.
The invention allows smaller achievable output transition times, a much simpler design and the good amplitude stability.
REFERENCES:
patent: 4228366 (1980-10-01), Huttemann et al.
patent: 5006739 (1991-04-01), Kimura et al.
patent: 5311141 (1994-05-01), Umeyama et al.
patent: 5742494 (1998-04-01), Brakus et al.
patent: 5874837 (1999-02-01), Manohar et al.
patent: 6028459 (2000-02-01), Birdsall et al.
patent: 6121805 (2000-09-01), Thamsirianunt et al.
patent: 0499175A2 (1992-02-01), None
patent: 1 430 397 (1973-12-01), None
Koffmane Gerd
Lazar Alexander
Agilent Technologie,s Inc.
Callahan Timothy P.
Nguyen Linh
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