Slope and level trim DAC for voltage reference

Details Slope and level trim DAC for voltage reference Slope and level trim DAC for voltage reference

1999-10-13

2001-12-11

Wong, Peter S. (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S314000

Reexamination Certificate

active

06329804

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of CMOS voltage references, and more particularly to a method and apparatus for performing slope and level trim in a voltage reference.
2. Description of the Related Art
Using a CMOS process to make a voltage reference has cost advantages over a precision-trimmed bipolar process. Problems with the accuracy and stability of CMOS devices must be overcome, however, in order to make a CMOS reference competitive in performance with bipolar references. Specifically, the lack of high-value stable and trimmable resistors presents a problem for circuit designers.
In order to adjust for variances in each circuit, voltage references are “trimmed” after manufacture in order to bring the output values within a specified range. This is generally accomplished by using lasers to etch away certain thin-film resistors (thereby increasing the resistance by decreasing the cross-sectional area). With proper design, most devices can be brought within the specified range using this technique. However, once the device (i.e. silicon die) is placed into a package, the mechanical stresses caused by the packaging can once again cause the circuit parameters to vary. Therefore, a competitive CMOS voltage reference must be designed such that the circuit may be “trimmed” after the final assembly of the die into a package.
One possible solution is to provide a series of resistors that can be switched in or out, as necessary, after final assembly in order to trim the slope and level of the output. This solution requires a large array of MOS switches, which have large resistance when the supply voltage is low. This resistance was found to contribute significant errors to the final reference voltage-errors that had variations with process and temperature and supply unrelated to the normal variations in the core cell. Another difficulty with using analog switches for trimming is that it is very cumbersome to change the trim range. This might be necessary, for example, in a reference with multiple voltage level options where multiple ranges of trim current are required.
Thus, it would be desirable to have an improved slope and level trim technique, suitable for use with CMOS voltage references, and providing post assembly trim.
SUMMARY OF THE INVENTION
The present invention is a method and apparatus for trimming the level and slope in a voltage reference. The present invention uses current-switching DACs to source (or sink) small correction currents into (from) the voltage reference circuit. Each DAC is controlled via a programmable non-volatile memory, which can be programmed after final packaging.
For the slope trim, the current is injected into (or drawn from) one side or the other of the band-gap core cell. The level trim DAC injects a correction current into (or draws a correction current from) the resistor chain that sets the voltage level at the base of the transistors in the band-gap core. The level and slope trim DACs generate or draw currents that arc precise multiples of the currents through the resistors being trimmed, via current mirrors. Thus the corrections are invariant with process and temperature, the necessary trim range is minimized, and the shape of the remaining error (curvature) is not altered. This current replication technique has the same effect as an ideal trim, i.e. produces the same result as changing the values of the resistors around which the trim circuits are placed.
The present invention trims the voltage reference without using switches in the main a circuit path. Also, the present technique enables trimming the voltage reference circuit after the circuit has been packaged, providing for better circuit calibration.


REFERENCES:
patent: 3887863 (1975-06-01), Brokaw
patent: 4190805 (1980-02-01), Bingham
patent: 4250445 (1981-02-01), Brokaw
patent: 4543522 (1985-09-01), Morean
patent: 4603291 (1986-07-01), Nelson
patent: 4613809 (1986-09-01), Skovmand
patent: 4792747 (1988-12-01), Schroeder
patent: 4803612 (1989-02-01), Skovmand
patent: 4808908 (1989-02-01), Lewis et al.
patent: 4902959 (1990-02-01), Brokaw
patent: 4906913 (1990-03-01), Stanojevic
patent: 4926109 (1990-05-01), Koterasawa
patent: 4928056 (1990-05-01), Pease
patent: 5126653 (1992-06-01), Ganesan et al.
patent: 5168209 (1992-12-01), Thiel
patent: 5191278 (1993-03-01), Carpenter
patent: 5274323 (1993-12-01), Dobkin et al.
patent: 5291122 (1994-03-01), Audy
patent: 5325045 (1994-06-01), Sundby
patent: 5334928 (1994-08-01), Dobkin et al.
patent: 5352973 (1994-10-01), Audy
patent: 5391980 (1995-02-01), Thiel et al.
patent: 5410241 (1995-04-01), Cecil
patent: 5485109 (1996-01-01), Dobkin et al.
patent: 5510697 (1996-04-01), Dormer
patent: 5519308 (1996-05-01), Gilbert
patent: 5563504 (1996-10-01), Gilbert et al.
patent: 5629609 (1997-05-01), Nguyen et al.
patent: 5631598 (1997-05-01), Miranda et al.
patent: 5672959 (1997-09-01), Der
patent: 5675241 (1997-10-01), Teggatz et al.
patent: 5677558 (1997-10-01), McGlinchey
patent: 5686821 (1997-11-01), Brokaw
patent: 5705919 (1998-01-01), Wilcox
patent: 5736843 (1998-04-01), Amin
patent: 5814979 (1998-09-01), Grimm
patent: 5867015 (1999-02-01), Corsi et al.
B. Song and P.R. Gray, “A Precision Curvature-Compensated CMOS Bandgap Reference,”JSSC, pp. 634-643, Dec. 1983.
Holman, Timothy, “A New Temperature Compensation Technique for Bandgap Voltage References,”ISCAS, pp. 385-388, 1996.
Rincon-Mora, G.A. and Allen, P.E., A 1.1V Current_Mode and Piecewise-Linear Curvature-Corrected Bandgap Reference,JSSC, pp. 1551-1554.
Gray, P.R. and Meyer, R.G., “Band-Gap Referenced Biasing Circuits,” section A4.3.2 inAnalysis and Design of Analog Integrated Circuits, 3rded.
Sze, S.M., “Carrier Transport Phenomena,” section 1.5 inPhysics of Semiconductor Devices, 2nded. (Wiley, 1981).
Annema, Anne-Johan, “Low-Power Bandgap References Featuring DTMOST's,”IEEE Journal of Solid-State Circuits, vol. 34, No. 7, pp. 949-955, Jul. 1999.
Banba, Hironori et al., “A CMOS Bandgap Reference Circuit with Sub-1-V Operation,”IEEE Journal of Solid-State Circuits, vol. 34, No. 5, pp. 670-673, May 1999.
Sudha, Maramreddy and Holman, W. Timothy, “A Low Noise Sub-Bandgap Voltage Reference,”IEEE, pp. 193-196, 1997.
Pease, Robert A., “The Design of Band-Gap Reference Circuits: Trials and Tribulations,”IEEE 1990 Bipolar Circuits and Technology Meeting 9.3, pp. 214-218.
Lin, S.L. and C.A.T. Salama, “Regular Correspondence,”IEEE Journal of Solid-State Circuits, vol. SC-20, No. 6, pp. 1283-1285, Dec. 1985.
Michejda, John and Kim, Suk. K., “A Precision CMOS Bandgap Reference,”IEEE Journal of Solid-State Circuits, vol. SC-19, No. 6, pp. 1014-1021, Dec. 1984.
Palmer, Carl R. and Dobkin, Robert C., “A Curvature Corrected Micropower Voltage Reference,”Session VI: Data Acquisition Circuits, ISSCC 81, pp. 58-59, Feb. 18, 1981.
Frederiksen, Thomas M., “Intuitive IC OP Amps,” FromBAsics to Useful Applications,National's Semiconductor Technology Series, pp. 8-12, 1984.
“IC Preamplifier Challenges Choppers on Drift,”National Semiconductor, Application Notes 79-81, pp. 279-281.

Affiliated with

Also associated with

Rating

Slope and level trim DAC for voltage reference does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Slope and level trim DAC for voltage reference, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Slope and level trim DAC for voltage reference will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2596479